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HCS12 Datasheet(PDF) 327 Page - Freescale Semiconductor, Inc

Part # HCS12
Description  HCS12 Microcontrollers
PDF  452 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

HCS12 Datasheet(HTML) 327 Page - Freescale Semiconductor, Inc

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S12CPUV2 Reference Manual, Rev. 4.0
Freescale Semiconductor
327
8.3.3 Null (Code 0:0)
The 0:0 data movement state indicates that there was no data movement in
the instruction queue; the 0:0 execution start state indicates continuation of
an instruction or interrupt sequence (no new instruction or interrupt start).
8.3.4 LAT — Latch Data from Bus (Code 0:1)
This code is not used in the HCS12. In the M68HC12, fetched program
information has arrived, but the queue is not ready to advance. The
information is latched into a buffer. Later, when the queue does advance,
stage 1 is refilled from the buffer or from the data bus if the buffer is empty.
In some instruction sequences, there can be several latch cycles before the
queue advances. In these cases, the buffer is filled on the first latch event
and additional latch requests are ignored.
8.3.5 ALD — Advance and Load from Data Bus (Code 1:0)
The instruction queue is advanced by one word and stage one is refilled with
a word of program information from the data bus. The CPU requested the
information two bus cycles earlier but, due to access delays, the information
was not available until the E cycle referred to by the ALD code.
8.3.6 ALL — Advance and Load from Latch (Code 1:1)
This code is not used in the HCS12. In the M68HC12, the 2-stage instruction
queue is advanced by one word and stage one is refilled with a word of
program information from the buffer. The information was latched from the
data bus at the falling edge of a previous E cycle because the instruction
queue was not ready to advance when it arrived.
8.3.7 INT — Interrupt Sequence Start (Code 0:1)
The E cycle associated with this code is the first cycle of an interrupt
sequence. Normally, this cycle is a read of the interrupt vector. However, in
systems that have interrupt vectors in external memory and an 8-bit data
bus, this cycle reads the upper byte of the 16-bit interrupt vector.



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