HCS12 datasheet(331/452 Pages) FREESCALE

331 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

331

8.5 Queue Reconstruction (for M68HC12)

The raw signals required for queue reconstruction are the address bus

(ADDR), the data bus (DATA), the system clock (E), and the queue status

signals (IPIPE1 and IPIPE0). An E-clock cycle begins after an E fall.

Addresses and data movement status must be captured at the E rise in the

middle of the cycle. Data and execution start status must be captured at the

E fall at the end of the cycle. These captures can then be organized into

records with one record per E clock cycle.

Implementation details depend upon the type of device and the mode of

operation. For instance, the data bus can be eight bits or 16 bits wide, and

non-multiplexed or multiplexed. In all cases, the externally reconstructed

queue must use 16-bit words. Demultiplexing and assembly of 8-bit data

into 16-bit words is done before program information enters the real queue,

so it must also be done for the external reconstruction.

An example:

Systems with an 8-bit data bus and a program stored in external memory

require two cycles for each program word fetch. MCU bus control logic

freezes the CPU clocks long enough to do two 8-bit accesses rather than

a single 16-bit access, so the CPU sees only 16-bit words of program

information. To recover the 16-bit program words externally, latch the

data bus state at the falling edge of E when ADDR0 = 0, and gate the

outputs of the latch onto DATA[15:8] when a LAT or ALD cycle occurs.

Since the 8-bit data bus is connected to DATA[7:0], the 16-bit word on the

data lines corresponds to the ALD or LAT status indication at the E rise

after the second 8-bit fetch, which is always to an odd address. IPIPE1

and IPIPE0 status signals indicate 0:0 at the beginning (E fall) and middle

(E rise) of the first 8-bit fetch.

Some M68HC12 devices have address lines to support memory expansion

beyond the standard 64-Kbyte address space. When memory expansion is

used, expanded addresses must also be captured and maintained.

8.5.1 Queue Reconstruction Registers (for M68HC12)

Queue reconstruction requires these registers, which can be implemented

as software variables when previously captured trace data is used or as

hardware latches in real time.

HCS12 Datasheet(PDF) 331 Page - Freescale Semiconductor, Inc