HCS12 datasheet(323/452 Pages) FREESCALE

323 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

323

8.1 Introduction

This section describes development and debug support features related to

the central processor unit (CPU12). Topics include:

• Single-wire background debug interface

• Hardware breakpoint system

• Instruction queue operation and reconstruction

• Instruction tagging

1 = Valid Data

TRACE — Trace Flag

Indicates when tracing is enabled. Firmware in the BDM ROM sets

TRACE in response to a TRACE1 command and TRACE is cleared upon

completion of the TRACE1 command. Do not attempt to write TRACE

directly with WRITE_BD_BYTE commands.

0 = Tracing not enabled

1 = TRACE1 command in progress

8.2 External Reconstruction of the Queue

The CPU12 uses an instruction queue to buffer program information and

increase instruction throughput. The HCS12 implements the queue

somewhat differently from the original M68HC12. The HCS12 queue

consists of three 16-bit stages while the M68HC12 queue consists of two

16-bit stages, plus a 16-bit holding latch. Program information is always

fetched in aligned 16-bit words. At least three bytes of program information

are available to the CPU when instruction execution begins. The holding

latch in the M68HC12 is used when a word of program information arrives

before the queue can advance.

Reference Manual — S12CPUV2

Section 8.

Instruction Queue

HCS12 Datasheet(PDF) 323 Page - Freescale Semiconductor, Inc