HCS12 datasheet(405/452 Pages) FREESCALE

405 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

405

All of the translations produce the same amount of or slightly more object

code than the original M68HC11 instructions. However, there are offsetting

savings in other instructions. Y-indexed instructions in particular assemble

into one byte less object code than the same M68HC11 instruction.

The CPU12 has a 2-page opcode map, rather than the 4-page M68HC11

map. This is largely due to redesign of the indexed addressing modes. Most

of pages 2, 3, and 4 of the M68HC11 opcode map are required because

Y-indexed instructions use different opcodes than X-indexed instructions.

Approximately two-thirds of the M68HC11 page 1 opcodes are unchanged

in CPU12, and some M68HC11 opcodes have been moved to page 1 of the

CPU12 opcode map. Object code for each of the moved instructions is one

byte smaller than object code for the equivalent M68HC11 instruction.

Table B-2 shows instructions that assemble to one byte less object code on

the CPU12.

CLC

CLI

CLV

SEC

SEI

SEV

ANDCC #$FE

ANDCC #$EF

ANDCC #$FD

ORCC #$01

ORCC #$10

ORCC #$02

ANDCC and ORCC now allow more control

over the CCR, including the ability to set or

clear multiple bits in a single instruction. These

instructions take one byte each on M68HC11

while the ANDCC and ORCC equivalents take

two bytes each.

DES

INS

LEAS –1,S

LEAS 1,S

Unlike DEX and INX, DES and INS did not

affect CCR bits in the M68HC11, so the LEAS

equivalents in CPU12 duplicate the function of

DES and INS. These instructions are one byte

on M68HC11 and two bytes on CPU12.

TAP

TPA

TSX

TSY

TXS

TYS

XGDX

XGDY

TFR A,CCR

TFR CCR,A

TFR S,X

TFR S,Y

TFR X,S

TFR Y,S

EXG D,X

EXG D,Y

The M68HC11 has a small collection of specific

transfer and exchange instructions. CPU12

expanded this to allow transfer or exchange

between any two CPU registers. For all but TSY

and TYS (which take two bytes on either CPU),

the CPU12 transfer/exchange costs one extra

byte compared to the M68HC11. The substitute

instructions execute in one cycle rather than

two.

Table B-1. Translated M68HC11 Mnemonics (Continued)

M68HC11

Mnemonic

Equivalent

CPU12 Instruction

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