HCS12 datasheet(409/452 Pages) FREESCALE

409 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

409

been misaligned, the queue would be ready to advance and the O cycle

would be used to perform a program word fetch.

In a single-chip system or in a system with the program in 16-bit memory,

both the free cycle and the program fetch cycle take one bus cycle. In a

system with the program in an external 8-bit memory, the O cycle takes one

bus cycle when it appears as a free cycle, but it takes two bus cycles when

used to perform a program fetch. In this case, the on-chip integration

module freezes the CPU clocks long enough to perform the cycle as two

smaller accesses. The CPU handles only 16-bit data, and is not aware that

the 16-bit program access is split into two 8-bit accesses.

To allow development systems to track events in the CPU12 instruction

queue, two status signals (IPIPE[1:0]) provide information about data

movement in the queue and about the start of instruction execution. A

development system can use this information along with address and data

information to externally reconstruct the queue. This representation of the

queue can also track both the data and address buses.

B.5.3 Stack Function

Both the M68HC11 and the CPU12 stack nine bytes for interrupts. Since this

is an odd number of bytes, there is no practical way to ensure that the stack

will stay aligned. To ensure that instructions take a fixed number of cycles

regardless of stack alignment, the internal RAM in M68HC12 MCUs is

designed to allow single cycle 16-bit accesses to misaligned addresses. As

long as the stack is located in this special RAM, stacking and unstacking

operations take the same amount of execution time, regardless of stack

alignment. If the stack is located in an external 16-bit RAM, a PSHX

instruction can take two or three cycles depending on the alignment of the

stack. This extra access time is transparent to the CPU because the

integration module freezes the CPU clocks while it performs the extra 8-bit

bus cycle required for a misaligned stack operation.

The CPU12 has a “last-used” stack rather than a “next-available” stack like

the M68HC11 CPU. That is, the stack pointer points to the last 16-bit stack

address used, rather than to the address of the next available stack location.

This generally has very little effect, because it is very unusual to access

stacked information using absolute addressing. The change allows a 16-bit

word of data to be removed from the stack without changing the value of the

SP twice.

To illustrate, consider the operation of a PULX instruction. With the

next-available M68HC11 stack, if the SP = $01F0 when execution begins,

HCS12 Datasheet(PDF) 409 Page - Freescale Semiconductor, Inc