HCS12 datasheet(410/452 Pages) FREESCALE

410 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

410

Freescale Semiconductor

the sequence of operations is: SP = SP + 1; load X from $01F1:01F2; SP =

SP + 1; and the SP ends up at $01F2. With the last-used CPU12 stack, if

the SP = $01F0 when execution begins, the sequence is: load X from

$01F0:01F1; SP = SP + 2; and the SP again ends up at $01F2. The second

sequence requires one less stack pointer adjustment.

The stack pointer change also affects operation of the TSX and TXS

instructions. In the M68HC11, TSX increments the SP by one during the

transfer. This adjustment causes the X index to point to the last stack

location used. The TXS instruction operates similarly, except that it

decrements the SP by one during the transfer. CPU12 TSX and TXS

instructions are ordinary transfers — the CPU12 stack requires no

adjustment.

For ordinary use of the stack, such as pushes, pulls, and even

manipulations involving TSX and TXS, there are no differences in the way

the M68HC11 and the CPU12 stacks look to a programmer. However, the

stack change can affect a program algorithm in two subtle ways.

The LDS #$xxxx instruction is normally used to initialize the stack pointer at

the start of a program. In the M68HC11, the address specified in the LDS

instruction is the first stack location used. In the CPU12, however, the first

stack location used is one address lower than the address specified in the

LDS instruction. Since the stack builds downward, M68HC11 programs

reassembled for the CPU12 operate normally, but the program stack is one

physical address lower in memory.

In very uncommon situations, such as test programs used to verify CPU

operation, a program could initialize the SP, stack data, and then read the

stack via an extended mode read (it is normally improper to read stack data

from an absolute extended address). To make an M68HC11 source

program that contains such a sequence work on the CPU12, change either

the initial LDS #$xxxx or the absolute extended address used to read the

stack.

B.6 Improved Indexing

The CPU12 has significantly improved indexed addressing capability, yet

retains compatibility with the M68HC11. The one cycle and one byte cost of

doing Y-related indexing in the M68HC11 has been eliminated. In addition,

high-level language requirements, including stack relative indexing and the

ability to perform pointer arithmetic directly in the index registers, have been

accommodated.

HCS12 Datasheet(PDF) 410 Page - Freescale Semiconductor, Inc