HCS12 datasheet(407/452 Pages) FREESCALE

407 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

407

B.4 Programmer’s Model and Stacking

The CPU12 programming model and stacking order are identical to those of

the M68HC11.

B.5 True 16-Bit Architecture

The M68HC11 is a direct descendant of the M6800, one of the first

microprocessors, which was introduced in 1974. The M6800 was strictly an

8-bit machine, with 8-bit data buses and 8-bit instructions. As Freescale

devices evolved from the M6800 to the M68HC11, a number of 16-bit

instructions were added, but the data buses remained eight bits wide, so

these instructions were performed as sequences of 8-bit operations. The

CPU12 is a true 16-bit implementation, but it retains the ability to work with

the mostly 8-bit M68HC11 instruction set. The larger arithmetic logic unit

(ALU) of the CPU12 (it can perform some 20-bit operations) is used to

calculate 16-bit pointers and to speed up math operations.

B.5.1 Bus Structures

The CPU12 is a 16-bit processor with 16-bit data paths. Typical HCS12 and

M68HC12 devices have internal and external 16-bit data paths, but some

derivatives incorporate operating modes that allow for an 8-bit data bus, so

that a system can be built with low-cost 8-bit program memory. HCS12 and

M68HC12 MCUs include an on-chip integration module that manages the

external bus interface. When the CPU makes a 16-bit access to a resource

that is served by an 8-bit bus, the integration module performs two 8-bit

accesses, freezes the CPU clocks for part of the sequence, and assembles

the data into a 16-bit word. As far as the CPU is concerned, there is no

difference between this access and a 16-bit access to an internal resource

via the 16-bit data bus. This is similar to the way an M68HC11 can stretch

clock cycles to accommodate slow peripherals.

HCS12 Datasheet(PDF) 407 Page - Freescale Semiconductor, Inc