PSD4235G2V_09 datasheet(32/124 Pages) STMICROELECTRONICS

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Detailed operation

PSD4235G2V

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6.2

Primary Flash memory and secondary Flash memory

description

The primary Flash memory is divided evenly into 8 sectors. The secondary Flash memory is

divided evenly into 4 sectors. Each sector of either memory block can be separately

protected from Program and Erase cycles.

Flash memory may be erased on a sector-by-sector basis, and programmed word-by-word.

Flash sector erasure may be suspended while data is read from other sectors of the block

and then resumed after reading.

During a Program or Erase cycle in Flash memory, the status can be output on the

Ready/Busy pin (PE4). This pin is set up using PSDsoft Express.

6.2.1

Memory block Select signals

The DPLD generates the Select signals for all the internal memory blocks (see Section 15:

PLDS). Each of the sectors of the primary Flash memory has a Select signal (FS0-FS7)

which can contain up to three product terms. Each of the sectors of the secondary Flash

memory has a Select signal (CSBOOT0-CSBOOT3) which can contain up to three product

terms. Having three product terms for each Select signal allows a given sector to be

mapped in different areas of system memory. When using a MCU with separate Program

and Data space (80C51XA), these flexible Select signals allow dynamic re-mapping of

sectors from one memory space to the other before and after IAP. The SRAM block has a

single Select signal (RS0).

6.2.2

Ready/Busy (PE4)

This signal can be used to output the Ready/Busy status of the PSD. The output is a ’0’

(Busy) when a Flash memory block is being written to, or when a Flash memory block is

being erased. The output is a ’1’ (Ready) when no WRITE or Erase cycle is in progress.

6.3

Memory operation

The primary Flash memory and secondary Flash memory are addressed through the MCU

Bus Interface. The MCU can access these memories in one of two ways:

●

The MCU can execute a typical bus WRITE or READ operation just as it would if

accessing a RAM or ROM device using standard bus cycles.

●

The MCU can execute a specific instruction that consists of several WRITE and READ

operations. This involves writing specific data patterns to special addresses within the

Flash memory to invoke an embedded algorithm. These instructions are summarized in

Table 28.

Typically, the MCU can read Flash memory using READ operations, just as it would read a

ROM device. However, Flash memory can only be erased and programmed using specific

instructions. For example, the MCU cannot write a single byte directly to Flash memory as

one would write a byte to RAM. To program a word into Flash memory, the MCU must

execute a Program instruction, then test the status of the Programming event. This status

test is achieved by a READ operation or polling Ready/Busy (PE4).

Flash memory can also be read by using special instructions to retrieve particular Flash

device information (sector protect status and ID).

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