R5F52108ADFF datasheet(34/92 Pages) RENESAS

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R01DS0041EJ0050 Rev.0.50

Page 34 of 90

Apr 15, 2011

RX210 Group

2. CPU

Under development Preliminary document

Specifications in this document are tentative and subject to change.

2.3

Processor Mode

The RX CPU supports two processor modes, supervisor and user. These processor modes enable the realization of a

hierarchical CPU resource protection.

Each processor mode imposes a level on rights of access to the CPU resources and the instructions that can be executed.

Supervisor mode carries greater rights than those of user mode.

The initial state after a reset is supervisor mode.

2.3.1

Supervisor Mode

In supervisor mode, all CPU resources are accessible and all instructions are available. However, writing to the processor

mode select bit (PM) in the processor status word (PSW) by executing an MVTC or a POPC instruction will be ignored.

For details on how to write to the PM bit, refer to section 2.2.2.4, Processor Status Word (PSW).

2.3.2

User Mode

In user mode, write access to the CPU resources listed below is restricted. The restriction applies to any instruction

capable of write access.

 Some bits (bits IPL[3:0], PM, U, and I) in the processor status word (PSW)

 Interrupt stack pointer (ISP)

 Interrupt table register (INTB)

 Backup PSW (BPSW)

 Backup PC (BPC)

 Fast interrupt vector register (FINTV)

2.3.3

Privileged Instruction

Privileged instructions can only be executed in supervisor mode. Executing a privileged instruction in user mode

produces a privileged instruction exception. Privileged instructions include the RTFI, MVTIPL, RTE, and WAIT

instructions.

2.3.4

Switching Between Processor Modes

Manipulating the processor mode select bit (PM) in the processor status word (PSW) switches the processor mode.

However, rewriting to the PM bit by executing an MVTC or a POPC instruction is prohibited. Switch the processor mode

by following the procedures described below.

(1)

Switching from user mode to supervisor mode

After an exception has been generated, the PSW.PM bit is set to 0 and the CPU switches to supervisor mode. The

hardware pre-processing is executed in supervisor mode. The state of the processor mode before the exception was

generated is retained in the the copy of PSW.PM bit is saved on the stack.

(2)

Switching from supervisor mode to user mode

Executing an RTE instruction when the value of the copy of the PSW.PM bit that has been preserved on the stack is 1 or

an RTFI instruction when the value of the copy of the PSW.PM bit that has been preserved in the backup PSW (BPSW)

is 1 causes a transition to user mode. In the transition to user mode, the value of the stack pointer designation bit (the U

bit in the PSW) becomes 1.

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