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R5F52108ADFF Datasheet(PDF) 31 Page - Renesas Technology Corp |
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R5F52108ADFF Datasheet(HTML) 31 Page - Renesas Technology Corp |
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31 / 92 page ![]() R01DS0041EJ0050 Rev.0.50 Page 31 of 90 Apr 15, 2011 RX210 Group 2. CPU Under development Preliminary document Specifications in this document are tentative and subject to change. 2.2.2.4 Processor Status Word (PSW) Note 1. In user mode, writing to the IPL[3:0], PM, U, and I bits by an MVTC or a POPC instruction is ignored. Writing to the IPL[3:0] bits by an MVTIPL instruction generates a privileged instruction exception. Note 2. In supervisor mode, writing to the PM bit by an MVTC or a POPC instruction is ignored, but writing to the other bits is possible. Note 3. Switching from supervisor mode to user mode requires execution of an RTE instruction after having set the PSW.PM bit saved on the stack to 1 or executing an RTFI instruction after having set the BPSW.PM bit to 1. b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 ———— IPL[3:0] ——— PM —— U I Value after reset: 00000 0000000 0000 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 —————— —————— O S Z C Value after reset: 00000 0000000 0000 Bit Symbol Bit Name Description R/W b0 C Carry Flag 0: No carry has occurred. 1: A carry has occurred. R/W b1 Z Zero Flag 0: Result is non-zero. 1: Result is 0. R/W b2 S Sign Flag 0: Result is a positive value or 0. 1: Result is a negative value. R/W b3 O Overflow Flag 0: No overflow has occurred. 1: An overflow has occurred. R/W b15 to b4 — Reserved These bits are always read as 0. The write value should be 0. R/W b16 I*1 Interrupt Enable 0: Interrupt disabled. 1: Interrupt enabled. R/W b17 U*1 Stack Pointer Select 0: Interrupt stack pointer (ISP) is selected. 1: User stack pointer (USP) is selected. R/W b19, b18 — Reserved These bits are always read as 0. The write value should be 0. R/W b20 PM*1,*2,*3 Processor Mode Select 0: Supervisor mode is selected. 1: User mode is selected. R/W b23 to b21 — Reserved These bits are always read as 0. The write value should be 0. R/W b27 to b24 IPL[3:0]*1 Processor Interrupt Priority Level b27 b24 0 0 0 0: Priority level 0 (lowest) 0 0 0 1: Priority level 1 0 0 1 0: Priority level 2 0 0 1 1: Priority level 3 0 1 0 0: Priority level 4 0 1 0 1: Priority level 5 0 1 1 0: Priority level 6 0 1 1 1: Priority level 7 1 0 0 0: Priority level 8 1 0 0 1: Priority level 9 1 0 1 0: Priority level 10 1 0 1 1: Priority level 11 1 1 0 0: Priority level 12 1 1 0 1: Priority level 13 1 1 1 0: Priority level 14 1 1 1 1: Priority level 15 (highest) R/W b31 to b28 — Reserved These bits are always read as 0. The write value should be 0. R/W |
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