CY8C20121 datasheet(7/43 Pages) CYPRESS

7 / 43 page

CY8C20111, CY8C20121

Document Number: 001-53516 Rev. *G

Page 7 of 43

7.2 I2C Clock Stretching

“Clock stretching” or “bus stalling” in I2C communication protocol

is a state in which the slave holds the SCL line low to indicate

that it is busy. In this condition, the master is expected to wait

until the SCL is released by the slave.

When an I2C master communicates with the CapSense Express

device, the CapSense Express stalls the I2C bus after the

reception of each byte (that is, just before the ACK/NAK bit) until

processing of the byte is complete and critical internal functions

are executed. Use a fully I2C compliant master to communicate

with the CapSense Express device.

An I2C master which does not support clock stretching (a bit

banged software I2C Master) must wait for a specific amount of

time specified (as shown in the section Format for Register Write

and Read) for each register write and read operation before the

next bit is transmitted. It is mandatory to check the SCL status (it

should be high) before I2C master initiates any data transfer with

CapSense Express. If the master fails to do so and continues to

communicate, the communication is erroneous.

The following diagrams represent the ACK time delays shown in

the Register Map on page 7.

Figure 3. Write ACK Time Representation

Figure 4. Read ACK Time Representation

7.3 Format for Register Write and Read

Legends:

8. Registers

Table 4. Register Conventions

Start

Slave Addr + W

AReg Addr

AData

. . . . .

Data

Stop

Start

Slave Addr + W

AReg Addr

AStop

Start

Slave Addr + R

Data

. . . . .

Data

NStop

Master

A - ACK

Slave

N- NAK

Convention

Description

WPR

Write register with pass code

Factory defaults

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