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PIC24F04KA201 Datasheet(PDF) 28 Page - Microchip Technology |
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PIC24F04KA201 Datasheet(HTML) 28 Page - Microchip Technology |
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28 / 48 page  PIC24FXXKAXXX DS39919A-page 28 Advance Information © 2008 Microchip Technology Inc. 4.7.3 CODE-PROTECT CONFIGURATION BITS The FBS and FGS Configuration registers are special Configuration registers which control the code protection for the boot segment and general segment, respectively. For each segment, two forms of code protection are provided. One form prevents code memory from being written (write protection), while the other prevents it from being read (read protection). The BWRP and GWRP bits control write protection and the BSS0 and GSS0 bits control read protection. When write protection is enabled, any programming operation to code memory will fail. When read protection is enabled, any read from code memory will cause a 00h to be read, regardless of the actual contents of code memory. Since the programming executive always verifies what it programs, attempting to program code memory with read protection enabled also results in failure. It is imperative that all code protection bits should be ‘1’ while the device is being programmed, and verified. Only after the device is programmed and verified should any of the above bits be programmed to ‘0’ (see Section 4.7 “Configuration Bits Programming”). Note: All bits in the FBS and FGS Configuration registers can only be programmed to a value of ‘0‘.Bulk Erasing the chip is the only way to reprogram code-protect bits from on (‘0’) to off (‘1’). TABLE 4-2: PIC24FXXKAXXX FAMILY CONFIGURATION BITS DESCRIPTION Bit Field Register Description BOREN<1:0> FPOR<1:0> Brown-out Reset Enable bits 11 = Brown-out Reset enabled in hardware; SBOREN bit disabled 10 = Brown-out Reset enabled only while device is active and disabled in Sleep; SBOREN bit disabled 01 = Brown-out Reset controlled with the SBOREN bit setting 00 = Brown-out Reset disabled in hardware; SBOREN bit disabled BORV<1:0> FPOR<6:5> Brown-out Reset Voltage bits 11 = VBOR set to 1.8V min 10 = VBOR set to 2.0V min 01 = VBOR set to 2.7V min 00 = Downside protection on POR enabled – “Zero-power” selected BSS0 FBS<3> Boot Segment Program Flash Code Protection bit 1 = No protection 0 = Standard security enabled BSZ<1:0> FBS<2:1> Boot Segment Program Flash Size Selection bits 11 = No boot program Flash segment 10 = Boot program Flash segment starts at 200h, ends at 000AFEh 01 = Boot program Flash segment starts at 200h, ends at 0015FEh 00 = Reserved BWRP FBS<0> Boot Segment Program Flash Write Protection bit 1 = Boot segment may be written 0 = Boot segment is write-protected DEBUG FICD<7> Background Debugger Enable bit 1 = Background debugger disabled 0 = Background debugger functions enabled DSWDTEN FDS<7> Deep Sleep Watchdog Timer Enable bit 1 = DSWDT enabled 0 = DSWDT disabled DSWCKSEL FDS<4> DSWDT Reference Clock Select bit 1 = DSWDT uses LPRC as reference clock 0 = DSWDT uses SOSC as reference clock Note 1: Applies only to the 28-pin device. 2: The MCLRE fuse can only be changed when using the VPP-Based Test mode entry. This prevents a user from accidentally locking out the device from low-voltage test entry. |
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