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BD9102FVM BD9104FVM BD9106FVM

Datasheet

02.MAR.2012 Rev.001

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© 2011 ROHM Co., Ltd. All rights reserved.

TSZ22111･15･001

TSZ02201-0J3J0AJ00080-1-2

4. Determination of RITH, CITH that works as a phase compensator

As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area

due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high

frequency area due to the output capacitor and its ESR.

So, the phases are easily compensated by adding a zero to the

power amplifier output with C and R as described below to cancel a pole at the power amplifier.

Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load

resistance with CR zero correction by the error amplifier.

5. Determination of output voltage (for BD9106FVM only)

With R1 and R2 adjusted, the output voltage may be determined

as required.(Adjustable output voltage range： 1.0V to 2.5V)

Use 1 kΩ to 100 kΩ resistor for R1.

If a resistor of the

resistance higher than10

0 kΩ is used, check the assembled set

carefully for ripple voltage etc.

Fig.57 Determination of output voltage

Gain

[dB]

Phase

[deg]

Fig.54 Open loop gain characteristics

A

0

0

-90

A

0

0

-90

fz(Amp.)

Fig.55 Error amp phase compensation characteristics

fp=

1

1

Pole at power amplifier

When the output current decreases, the load resistance Ro

increases and the pole frequency lowers.

OMax.

1

[Hz]←with lighter load

OMin.

1

[Hz]←with heavier load

Zero at power amplifier

Increasing capacitance of the output capacitor lowers the

pole frequency while the zero frequency does not change.

(This is because when the capacitance is doubled, the

capacitor ESR reduces to half.)

ITH.

1

GND,PGND

SW

EN

ITH

Cin

L

ESR

Fig.56 Typical application

1

=

1

SW

6

1

ADJ

4.7μH

10μF

R2

R1

Output

fp(Min.)

fp(Max.)

fz(ESR)

Gain

[dB]

Phase

[deg]