V62SLASH04754-03YA datasheet(21/109 Pages) TI1

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SM320C6712EP, SM320C6712CEP, SM320C6712DEP

FLOATINGPOINT DIGITAL SIGNAL PROCESSORS

SGUS055 − SEPTEMBER 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

Terminal Functions

SIGNAL

PIN NO.

TYPE†

IPD/

‡

DESCRIPTION

SIGNAL

NAME

GFN

GDP

TYPE†

IPD/

IPU‡

DESCRIPTION

CLOCK/PLL

CLKIN

IPU

Clock Input

CLKOUT1

—

IPD

Clock output at device speed [C6712 only]

The CLK1EN bit in the EMIF GBLCTL register controls the CLKOUT1 pin.

CLK1EN = 0:

CLKOUT1 is disabled

CLK1EN = 1:

CLKOUT1 enabled to clock [default]

CLKOUT2

Y12

O/Z

IPD

Clock output at half of device speed [C6712 only]

For the C6712C/12D device, the CLKOUT2 pin is multiplexed with the GP[2] pin.

Clock output at half of device speed (O/Z) [default] (SYSCLK2 internal signal from the

clock generator) or this pin can be programmed as GP[2] (I/O/Z).

When the CLKOUT2 pin is enabled, the CLK2EN bit in the EMIF global control

CLK2EN = 0:

CLKOUT2 is disabled

CLK2EN = 1:

CLKOUT2 enabled to clock [default]

CLKOUT3

—

D10

IPD

Clock output programmable by OSCDIV1 register in the PLL controller. [12C/12D]

CLKMODE0

IPU

Clock mode select [C6712]

−

Bypass mode (x1). CPU clock = CLKIN

−

PLL mode (x4). CPU clock = 4 x CLKIN [default]

Clock generator input clock source select [C6712C/12D]

−

Reserved. Do not use.

−

CLKIN square wave [default]

For proper C6712C/12D device operation, this pin must be either left unconnected or

externally pulled up with a 1-k

Ω resistor.

PLLV§

—

A¶

PLL analog VCC connection for the low-pass filter [C6712 only]

PLLG§

—

A¶

PLL analog GND connection for the low-pass filter [C6712 only]

PLLF

—

A¶

PLL low-pass filter connection to external components and a bypass capacitor

[C6712 only]

PLLHV

—

A¶

Analog power (3.3 V) for PLL [C6712C/C6712D only]

JTAG EMULATION

TMS

IPU

JTAG test-port mode select

TDO

O/Z

IPU

JTAG test-port data out

TDI

IPU

JTAG test-port data in

TCK

IPU

JTAG test-port clock

TRST

IPD

JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1

JTAG Compatibility Statement section of this data sheet.

EMU5

B12

I/O/Z

IPU

Emulation pin 5. Reserved for future use, leave unconnected.

EMU4

C11

I/O/Z

IPU

Emulation pin 4. Reserved for future use, leave unconnected.

EMU3

B10

I/O/Z

IPU

Emulation pin 3. Reserved for future use, leave unconnected.

EMU2

D10

I/O/Z

IPU

Emulation pin 2. Reserved for future use, leave unconnected.

† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground

‡ For C6712, IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal

to the opposite supply rail, a 1-k

Ω resistor should be used.)

For C6712C/12D, IPD = Internal pulldown, IPU = Internal pullup. [These IPD/IPU signal pins feature a 13-k

Ω resistor (approximate) for the IPD

or 18-k

Ω resistor (approximate) for the IPU. An external pullup or pulldown resistor no greater than 4.4 kΩ and 2.0 kΩ, respectively, should be

used to pull a signal to the opposite supply rail.]

§ PLLV and PLLG are not part of external voltage supply or ground. See the clock/PLL section for information on how to connect these pins.

¶ A = Analog signal (PLL Filter)

V62/04754-03YA Datasheet(PDF) 21 Page - Texas Instruments

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