12

Integrated Silicon Solution, Inc. — www.issi.com

Rev. D

06/21/2011

IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,

IS64WV12816DBLL/DBLS

-8

-10

-12

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

WriteCycleTime

8

—

10

—

12

—

ns

CEtoWriteEnd

6.5

—

8

—

9

—

ns

AddressSetupTime

6.5

—

8

—

9

—

ns

toWriteEnd

AddressHoldfromWriteEnd

0

—

0

—

0

—

ns

AddressSetupTime

0

—

0

—

0

—

ns

LB,UBValidtoEndofWrite

6.5

—

8

—

9

—

ns

WEPulseWidth

6.5

—

8

—

9

—

ns

WEPulseWidth (OE=LOW)

8.0

—

10

—

11

—

ns

DataSetuptoWriteEnd

5

—

6

—

9

—

ns

DataHoldfromWriteEnd

0

—

0

—

0

—

ns

WELOWtoHigh-ZOutput

—

3.5

—

5

—

6

ns

WEHIGHtoLow-ZOutput

2

—

2

—

3

—

ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to

3.0V and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of

CE LOW and UB or LB, and WE LOW. All signals must be in valid states

to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced

to the rising or falling edge of the signal that terminates the write. Shaded area product in development