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ST10F280 Datasheet(PDF) 200 Page - STMicroelectronics

Part # ST10F280
Description  16-bit MCU with MAC unit, 512 Kbyte Flash memory and 18 Kbyte RAM
PDF  239 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F280 Datasheet(HTML) 200 Page - STMicroelectronics

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Special function register overview
ST10F280
200/239
Doc ID 8673 Rev. 3
RP0H
Address:
0xF108h / 84h ESFR
Reset:
0x--XXh
Type:
R
RDYENx
READY Input Enable
0: External bus cycle is controlled by bit field MCTC only
1: External bus cycle is controlled by the READY input signal
RDYPOLx
Ready Active Level Control
0: Active level on the READY pin is low, bus cycle terminates with a ‘0’ on READY
pin,
1: Active level on the READY pin is high, bus cycle terminates with a ‘1’ on READY
pin.
CSRENx
Read Chip Select Enable
0: The CS signal is independent of the read command (RD)
1: The CS signal is generated for the duration of the read command
CSWENx
Write Chip Select Enable
0: The CS signal is independent of the write command (WR,WRL,WRH)
1: The CS signal is generated for the duration of the write command
15
14
13
12
11
10
9
8
76
543
21
0
--
----
--
CLKSEL
SALSEL
CSSEL
WRC
R (1)(2)
1.
RP0H.7 to RP0H.5 bits are loaded only during a long hardware reset. As pull-up resistors are active on
each Port P0H pins during reset, RP0H default value is "FFh"
2.
These bits are set according to Port 0 configuration during any reset sequence.
R (2)
R (2)
R(2)
WRC
Write Configuration Control
0: Pin WR acts as WRL, pin BHE acts as WRH
1: Pins WR and BHE retain their normal function
CSSEL
Chip Select Line Selection (Number of active CS outputs)
00: 3 CS lines: CS2...CS0
01: 2 CS lines: CS1...CS0
10: No CS lines at all
11: 5 CS lines: CS4...CS0 (Default without pull-downs)
SALSEL
Segment Address Line Selection (Number of active segment address outputs)
00: 4-bit segment address: A19...A16
01: No segment address lines at all
10: 8-bit segment address: A23...A16
11: 2-bit segment address: A17...A16 (Default without pull-downs)



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