WM8983GEFLSLASHV datasheet(72/124 Pages) WOLFSON

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WM8983

Production Data

PD, Rev 4.3, May 2010

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R49

Output control

SPKBOOST

0 = speaker gain = -1;

DC = AVDD1 / 2

1 = speaker gain = +1.5;

DC = 1.5 x AVDD1 / 2

Power

management

BUFDCOPEN

Dedicated buffer for DC level shifting

output stages when in 1.5x gain

boost configuration.

0 = Buffer disabled

1 = Buffer enabled (required for 1.5x

gain boost)

Table 43 Speaker Boost Stage Control

SPKBOOST

OUTPUT

STAGE GAIN

OUTPUT DC

LEVEL

OUTPUT STAGE

CONFIGURATION

1x (0dB)

AVDD1/2

Inverting

1.5x (3.52dB)

1.5xAVDD1/2

Non-inverting

Table 44 Output Boost Stage Details

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R43

Beep control

MUTERPGA2INV

Mute input to INVROUT2 mixer

INVROUT2

Invert ROUT2 output

3:1

BEEPVOL

000

AUXR input to ROUT2 inverter gain

000 = -15dB

001 = -12dB

010 = -9dB

011 = -6dB

100 = -3dB

101 = 0dB

110 = +3dB

111 = +6dB

BEEPEN

0 = mute AUXR beep input

1 = enable AUXR beep input

Table 45 AUXR – ROUT2 BEEP Mixer Function

ZERO CROSS TIMEOUT

A zero-cross timeout function is provided so that if zero cross is enabled on the input or output PGAs

the gain will automatically update after a timeout period if a zero cross has not occurred. This is

enabled by setting SLOWCLKEN. The timeout period is dependent on the clock input to the digital

and is equal to 2

21 * SYSCLK period.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Additional

Control

SLOWCLKEN

Slow clock enable.

0 = slow clock disabled

1 = slow clock enabled

Table 46 Timeout Clock Enable Control

Note: SLOWCLKEN is also used for the jack insert detect debounce circuit

WM8983GEFL/V Datasheet(PDF) 72 Page - Wolfson Microelectronics plc

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