PIC24FJ128GA310 datasheet(176/406 Pages) MICROCHIP

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PIC24FJ128GA310 FAMILY

DS39996F-page 176

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11.4.3.3

Mapping Limitations

The control schema of the Peripheral Pin Select is

extremely flexible. Other than systematic blocks that

prevent signal contention, caused by two physical pins

being configured as the same functional input or two

functional outputs configured as the same pin, there

are no hardware enforced lock outs. The flexibility

extends to the point of allowing a single input to drive

multiple peripherals or a single functional output to

drive multiple output pins.

11.4.3.4

Mapping Exceptions for

PIC24FJ128GA310 Family Devices

Although the PPS registers theoretically allow for up to

64 remappable I/O pins, not all of these are imple-

mented in all devices. For PIC24FJ128GA310 family

devices, the maximum number of remappable pins

available is 44, which includes 12 input only pins. In

addition, some pins in the RP and RPI sequences are

unimplemented in lower pin count devices. The

differences

available

remappable

pins

are

summarized in Table 11-5.

When developing applications that use remappable

pins, users should also keep these things in mind:

• For the RPINRx registers, bit combinations corre-

sponding to an unimplemented pin for a particular

device are treated as invalid; the corresponding

module will not have an input mapped to it. For all

PIC24FJ128GA310 family devices, this includes

all values greater than 43 (‘101011’).

• For RPORx registers, the bit fields corresponding

to an unimplemented pin will also be

unimplemented. Writing to these fields will have

no effect.

11.4.4

CONTROLLING CONFIGURATION

CHANGES

Because peripheral remapping can be changed during

run time, some restrictions on peripheral remapping

are needed to prevent accidental configuration

changes. PIC24F devices include three features to

prevent alterations to the peripheral map:

• Control register lock sequence

• Continuous state monitoring

• Configuration bit remapping lock

11.4.4.1

Control Register Lock

Under normal operation, writes to the RPINRx and

RPORx registers are not allowed. Attempted writes will

appear to execute normally, but the contents of the

registers will remain unchanged. To change these reg-

isters, they must be unlocked in hardware. The register

lock is controlled by the IOLOCK bit (OSCCON<6>).

Setting IOLOCK prevents writes to the control

registers; clearing IOLOCK allows writes.

To set or clear IOLOCK, a specific command sequence

must be executed:

Write 46h to OSCCON<7:0>.

Write 57h to OSCCON<7:0>.

Clear (or set) IOLOCK as a single operation.

Unlike the similar sequence with the oscillator’s LOCK

bit, IOLOCK remains in one state until changed. This

allows all of the Peripheral Pin Selects to be configured

with a single unlock sequence, followed by an update

to all control registers, then locked with a second lock

sequence.

11.4.4.2

Continuous State Monitoring

In addition to being protected from direct writes, the

contents of the RPINRx and RPORx registers are

constantly monitored in hardware by shadow registers.

If an unexpected change in any of the registers occurs

(such as cell disturbances caused by ESD or other

external events), a Configuration Mismatch Reset will

be triggered.

11.4.4.3

Configuration Bit Pin Select Lock

As an additional level of safety, the device can be con-

figured to prevent more than one write session to the

RPINRx and RPORx registers. The IOL1WAY

(CW2<4>) Configuration bit blocks the IOLOCK bit

from being cleared after it has been set once. If

IOLOCK remains set, the register unlock procedure will

not execute and the Peripheral Pin Select Control reg-

isters cannot be written to. The only way to clear the bit

and re-enable peripheral remapping is to perform a

device Reset.

In the default (unprogrammed) state, IOL1WAY is set,

restricting users to one write session. Programming

IOL1WAY allows users unlimited access (with the

proper use of the unlock sequence) to the Peripheral

Pin Select registers.

TABLE 11-5:

REMAPPABLE PIN EXCEPTIONS FOR PIC24FJ128GA310 FAMILY DEVICES

Device

RP Pins (I/O)

RPI Pins

Total

Unimplemented

Total

Unimplemented

PIC24FJXXXGA306

RP5, RP15, RP31

RPI32-36, RPI38-43

PIC24FJXXXGA308

RP15

RPI32, RPI39, RPI41

PIC24FJXXXGA310

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