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STM8L151C8T6 Datasheet(PDF) 52 Page - STMicroelectronics |
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STM8L151C8T6 Datasheet(HTML) 52 Page - STMicroelectronics |
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52 / 129 page ![]() Memory and register map STM8L15xx8, STM8L15xR6 52/129 Doc ID 17943 Rev 5 0x00 5380 DAC DAC_CH1CR1 DAC channel 1 control register 1 0x00 0x00 5381 DAC_CH1CR2 DAC channel 1 control register 2 0x00 0x00 5382 DAC_CH2CR1 DAC channel 2 control register 1 0x00 0x00 5383 DAC_CH2CR2 DAC channel 2 control register 2 0x00 0x00 5384 DAC_SWTRIG DAC software trigger register 0x00 0x00 5385 DAC_SR DAC status register 0x00 0x00 5386 to 0x00 5387 Reserved area (2 bytes) 0x00 5388 DAC DAC_CH1RDHRH DAC channel 1 right aligned data holding register high 0x00 0x00 5389 DAC_CH1RDHRL DAC channel 1 right aligned data holding register low 0x00 0x00 538A to 0x00 538B Reserved area (2 bytes) 0x00 538C DAC DAC_CH1LDHRH DAC channel 1 left aligned data holding register high 0x00 0x00 538D DAC DAC_CH1LDHRL DAC channel 1 left aligned data holding register low 0x00 0x00 538E to 0x00 538F Reserved area (2 bytes) 0x00 5390 DAC DAC_CH1DHR8 DAC channel 1 8-bit data holding register 0x00 0x00 5391 to 0x00 5393 Reserved area (3 bytes) 0x00 5394 DAC DAC_CH2RDHRH DAC channel 2 right aligned data holding register high 0x00 0x00 5395 DAC_CH2RDHRL DAC channel 2 right aligned data holding register low 0x00 0x00 5396 to 0x00 5397 Reserved area (2 bytes) 0x00 5398 DAC DAC_CH2LDHRH DAC channel 2 left aligned data holding register high 0x00 0x00 5399 DAC_CH2LDHRL DAC channel 2 left aligned data holding register low 0x00 0x00 539A to 0x00 539B Reserved area (2 bytes) 0x00 539C DAC DAC_CH2DHR8 DAC channel 2 8-bit data holding register 0x00 0x00 539D to 0x00 539F Reserved area (3 bytes) Table 9. General hardware register map (continued) Address Block Register label Register name Reset status |
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