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STM8L151C8T6 Datasheet(PDF) 36 Page - STMicroelectronics

Part # STM8L151C8T6
Description  8-bit ultralow power MCU, up to 64 KB Flash 2 KB data EEPROM, RTC, LCD, timers, USARTs, I2C, SPIs, ADC, DAC, comparators
PDF  129 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM8L151C8T6 Datasheet(HTML) 36 Page - STMicroelectronics

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Pin description
STM8L15xx8, STM8L15xR6
36/129
Doc ID 17943 Rev 5
21 17
-
PG3/LCD SEG 31 (3)/
[TIM3_ETR]
I/O FT(5) X
XX HS X
X Port G3
LCD segment 31/
[Timer 3 - trigger]
33
PH4/USART2_RX
I/O FT(5) X
XX HS X
X Port H4 USART2 receive
34
PH5/USART2_TX
I/O FT(5) X
XX HS X
X Port H5 USART2 transmit
35
PH6/USART2_CK/
TIM5_CH1
I/O FT(5) X
XX HS X
X Port H6
USART2 synchronous
clock/ Timer 5 - channel 1
36
PH7/TIM5_CH2
I/O FT(5) X
XX HS X
X Port H7 Timer 5 - channel 2
-9 VSS/VSSA/VREF-
S
I/O ground / Analog ground voltage /
ADC1 negative voltage reference
13
9
- VSSA/VREF-
S
Analog ground voltage /
ADC1 negative voltage reference
37 29
- VDD3
S
IOs supply voltage
38 30
- VSS3
S
IOs ground voltage
51
1
PA0(8)/[USART1_CK](2)/
SWIM/BEEP/IR_TIM (9)
I/O
X
X
XHS X
X Port A0
[USART1 synchronous
clock](2) / SWIM input and
output / Beep output / Infra-
red Timer output
68 56 40 VSS2
IOs ground voltage
67 55 39 VDD2
IOs supply voltage
48
-
- VSS4
IOs ground voltage
47
-
- VDD4
IOs supply voltage
1.
At power-up, the PA1/NRST pin is a reset input pin with pull-up. To be used as a general purpose pin (PA1), it can be
configured only as output push-pull, not as output open-drain nor as a general purpose input. Refer to Section Configuring
NRST/PA1 pin as general purpose output in the STM8L15xx and STM8L16xx reference manual (RM0031).
2.
[ ] Alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function).
3.
Available on STM8L152xx devices only.
4.
A pull-up is applied to PB0 and PB4 during the reset phase. These two pins are input floating after reset release.
5.
In the 5 V tolerant I/Os, the protection diode to VDD is not implemented.
6.
In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to VDD are
not implemented).
7.
Available on STM8L152xx devices only. On STM8L151xx devices it is reserved and must be tied to VDD.
8.
The PA0 pin is in input pull-up during the reset phase and after reset release.
9.
High Sink LED driver capability available on PA0.
Table 5.
High density and medium+ density STM8L15x pin description (continued)
Pin
number
Pin name
Input
Output
Default alternate function



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