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MC68HSC705C8ACFS Datasheet(PDF) 71 Page - Freescale Semiconductor, Inc |
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MC68HSC705C8ACFS Datasheet(HTML) 71 Page - Freescale Semiconductor, Inc |
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71 / 222 page ![]() Low-Power Modes Stop Mode MC68HC705C8A — Rev. 3 Technical Data MOTOROLA Low-Power Modes 6.3.1 SCI During Stop Mode When the MCU enters stop mode, the baud rate generator stops, halting all SCI activity. If the STOP instruction is executed during a transmitter transfer, that transfer is halted. If a low input to the IRQ pin is used to exit stop mode, the transfer resumes. If the SCI receiver is receiving data and stop mode is entered, received data sampling stops because the baud rate generator stops, and all subsequent data is lost. Therefore, all SCI transfers should be in the idle state when the STOP instruction is executed. 6.3.2 SPI During Stop Mode When the MCU enters stop mode, the baud rate generator stops, terminating all master mode SPI operations. If the STOP instruction is executed during an SPI transfer, that transfer halts until the MCU exits stop mode by a low signal on the IRQ pin. If reset is used to exit stop mode, the SPI control and status bits are cleared, and the SPI is disabled. If the MCU is in slave mode when the STOP instruction is executed, the slave SPI continues to operate and can still accept data and clock information in addition to transmitting its own data back to a master device. At the end of a possible transmission with a slave SPI in stop mode, no flags are set until a low on the IRQ pin wakes up the MCU. NOTE: Although a slave SPI in stop mode can exchange data with a master SPI, the status bits of a slave SPI are inactive in stop mode. 6.3.3 Programmable COP Watchdog in Stop Mode The STOP instruction turns off the internal oscillator and suspends the computer operating properly (COP) watchdog counter. If the RESET pin brings the MCU out of stop mode, the reset function clears and disables the COP watchdog. If the IRQ pin brings the MCU out of stop mode, the COP counter resumes counting from its suspended value after the 4064-t CYC clock stabilization delay. See Figure 6-2. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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