| Electronic Components Datasheet Search |
|
MC68HSC705C8ACFS Datasheet(PDF) 79 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MC68HSC705C8ACFS Datasheet(HTML) 79 Page - Freescale Semiconductor, Inc |
|
79 / 222 page ![]() Parallel Input/Output (I/O) Port A MC68HC705C8A — Rev. 3 Technical Data MOTOROLA Parallel Input/Output (I/O) 7.3.2 Data Direction Register A The contents of data direction register A (DDRA) shown in Figure 7-2 determine whether each port A pin is an input or an output. Writing a logic 1 to a DDRA bit enables the output buffer for the associated port A pin; a logic 0 disables the output buffer. A reset clears all DDRA bits, configuring all port A pins as inputs. DDRA7–DDRA0 — Port A Data Direction Bits These read/write bits control port A data direction. Reset clears bits DDRA7–DDRA0. 1 = Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input NOTE: Avoid glitches on port A pins by writing to the port A data register before changing DDRA bits from logic 0 to logic 1. Address: $0004 Bit 7 6 54321 Bit 0 Read: DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 Write: Reset: 00 000000 Figure 7-2. Data Direction Register A (DDRA) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |