AD5429/AD5439/AD5449

Rev. C | Page 6 of 32

DB15

(N)

DB15

(N + 1)

DB0

(N)

DB0

(N + 1)

DB15

(N)

DB0

(N)

SCLK

SYNC

SDIN

SDO

NOTES

1. ALTERNATIVELY, DATA CAN BE CLOCKED INTO THE INPUT SHIFT REGISTER ON THE RISING EDGE OF SCLK AS

DETERMINED BY THE CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON THE FALLING

EDGE OF SCLK. TIMING IS AS ABOVE, WITH SCLK INVERTED.

Figure 3. Daisy-Chain Timing Diagram

SDO

SDIN

SYNC

SCLK

16

32

DB15

DB0

DB15

DB0

DB15

UNDEFINED

NOP CONDITION

DB0

INPUT WORD SPECIFIES

REGISTER TO BE READ

SELECTED REGISTER DATA

CLOCKED OUT

Figure 4. Readback Mode Timing Diagram

200

200

TO OUTPUT

PIN

50pF

2

Figure 5. Load Circuit for SDO Timing Specifications