EVAL-AD5449EBZ datasheet(22/32 Pages) AD

22 / 32 page

AD5429/AD5439/AD5449

Rev. C | Page 22 of 32

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD54xx family of DACs is

through a serial bus that uses standard protocol and is compatible

with microcontrollers and DSP processors. The communication

channel is a 3-wire interface consisting of a clock signal, a data

signal, and a synchronization signal. The AD5429/AD5439/

AD5449 require a 16-bit word, with the default being data valid

on the falling edge of SCLK; however, this is changeable using

the control bits in the data-word.

ADSP-21xx-to-AD5429/AD5439/AD5449 Interface

The ADSP-21xx family of DSPs is easily interfaced to an AD5429/

AD5439/AD5449 DAC without the need for extra glue logic.

Figure 48 is an example of a serial peripheral interface (SPI)

between the DAC and the ADSP-2191. The MOSI (master output,

slave input) pin of the DSP drives the serial data line, SDIN.

SYNC is driven from a port line, in this case SPIxSEL.

SCLK

SCK

SYNC

SPIxSEL

SDIN

MOSI

ADSP-2191*

*ADDITIONAL PINS OMITTED FOR CLARITY.

AD5429/AD5439/

AD5449*

Figure 48. ADSP-2191 SPI-to-AD5429/AD5439/AD5449 Interface

The ADSP-2101/ADSP-2103/ADSP-2191 processor incorporates

channel synchronous serial ports (SPORT). A serial interface

between the DAC and DSP SPORT is shown in Figure 49. In this

interface example, SPORT0 is used to transfer data to the DAC

shift register. Transmission is initiated by writing a word to the Tx

is clocked out on each rising edge of the DSP serial clock and

clocked into the DAC input shift register on the falling edge of

its SCLK. Updating of the DAC output takes place on the rising

edge of the SYNC signal.

SCLK

SYNC

TFS

SDIN

ADSP-2101/

ADSP-2103/

ADSP-2191

*ADDITIONAL PINS OMITTED FOR CLARITY.

AD5429/AD5439/

AD5449*

Figure 49. ADSP-2101/ADSP-2103/ADSP-2191 SPORT-to-

AD5429/AD5439/AD5449 Interface

Communication between two devices at a given clock speed is

possible when the following specifications are compatible: frame

SYNC delay and frame SYNC setup-and-hold, data delay and

data setup-and-hold, and SCLK width. The DAC interface expects

a t4 (SYNC falling edge to SCLK falling edge setup time) of 13 ns

minimum.

See the ADSP-21xx user manual at www.analog.com for details

on clock and frame SYNC frequencies for the SPORT register.

shows the setup for the SPORT control register.

Table 12

Table 12. SPORT Control Register Setup

Name

Setting

Description

TFSW

Alternate framing

INVTFS

Active low frame signal

DTYPE

Right-justify data

ISCLK

Internal serial clock

TFSR

Frame every word

ITFS

Internal framing signal

SLEN

1111

16-bit data-word

ADSP-BF5xx-to-AD5429/AD5439/AD5449 Interface

The ADSP-BF5xx family of processors has an SPI-compatible port

that enables the processor to communicate with SPI-compatible

devices. A serial interface between the BlackFin® processor and

the AD5429/AD5439/AD5449 DAC is shown in Figure 50. In

this configuration, data is transferred through the MOSI pin.

SYNC is driven by the SPIxSEL pin, which is a reconfigured

programmable flag pin.

SCLK

SCK

SYNC

SPIxSEL

SDIN

MOSI

ADSP-BF5xx*

*ADDITIONAL PINS OMITTED FOR CLARITY.

AD5429/AD5439/

AD5449*

Figure 50. ADSP-BF5xx-to-AD5429/AD5439/AD5449 Interface

A serial interface between the DAC and the DSP SPORT is shown

in Figure 51. When SPORT is enabled, initiate transmission by

writing a word to the Tx register. The data is clocked out on each

rising edge of the DSP serial clock and clocked into the DAC

input shift register on the falling edge of its SCLK. The DAC

output is updated by using the transmit frame synchronization

(TFS) line to provide a SYNC signal.

SCLK

SYNC

TFS

SDIN

ADSP-BF5xx*

*ADDITIONAL PINS OMITTED FOR CLARITY.

AD5429/AD5439/

AD5449*

Figure 51. ADSP-BF5xx SPORT-to-AD5429/AD5439/AD5449 Interface

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