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TMP86FS49FG

2.3.2 Address trap reset

If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction

from the on-chip RAM (when WDTCR1<ATAS> is set to “1”), DBR or the SFR area, address trap reset will

be generated. The reset time is about 8/fc to 24/fc [s] (0.5 to 1.5

µs at 16.0 MHz).

Note:The operating mode under address trapped is alternative of reset or interrupt. The address trap area is alter-

native.

Note 1: Address “a” is in the SFR or on-chip RAM (WDTCR1<ATAS> = “1”) space.

Note 2: During reset release, reset vector “r” is read out, and an instruction at address “r” is fetched and decoded.

Figure 2-16 Address Trap Reset

2.3.3 Watchdog timer reset

Refer to 2.4 “Watchdog Timer”.

2.3.4 System clock reset

Clearing both XEN and XTEN (Bits 7 and 6 in SYSCR2) to “0”, clearing XEN to “0” when SYSCK = “0”,

or clearing XTEN to “0” when SYSCK = “1” stops system clock, and causes the microcomputer to deadlock.

This can be prevented by automatically generating a reset signal whenever XEN = XTEN = “0”, XEN =

SYSCK = “0”, or XTEN = “0”/SYSCK = “1” is detected to continue the oscillation. The reset time is about 8/

fc to 24/fc [s] (0.5 to 1.5

µs at 16.0 MHz).

Instruction at address r

16/fc [s]

8/fc to 24/fc [s]

Instruction

execution

Internal reset

JP

a

Reset release

Address trap is occurred

4/fc to 12/fc [s]

TENTATIVE