TMP86FS49FG datasheet(11/42 Pages) TOSHIBA

11 / 42 page

Page 9

TMP86FS49FG

2. Operational Description

2.1 CPU Core Functions

The CPU core consists of a CPU, a system clock controller, and an interrupt controller.

This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit.

2.1.1 Memory Address Map

The TMP86FS49FG memory consists of 4 blocks: FLASH, RAM, DBR (Data buffer register) and SFR

(Special function register). They are all mapped in 64-Kbyte address space. Figure 2-1 shows the

TMP86FS49FG memory address map. The general-purpose registers are not assigned to the RAM address

space.

Figure 2-1 Memory Address Map

64 byte

SFR

RAM

DBR

0040H

2Kbyte

083FH

0F80H

0FFFH

1000H

FFFFH

FLASH

60Kbyte

FLASH

: includes;

Program memory

Vector table

RAM: Random access memory includes:

Data memory

Stack

SFR:

Special function register includes:

I/O ports

Peripheral control registers

Peripheral status registers

System control registers

Program status word

DBR:

Databuffer register includes:

Peripheral status registers

003FH

0000H

FFA0H

128byte

TENTATIVE

TMP86FS49FG Datasheet(PDF) 11 Page - Toshiba Semiconductor

TMP86FS49FG Datasheet(HTML) 11 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Datasheet Download

Link URL