TMP86FS49FG datasheet(12/42 Pages) TOSHIBA

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2. Operational Description

2.2 System Clock Controller

TMP86FS49FG

2.1.2 Program Memory (FLASH)

The TMP86FS49FG has a 60K

× 8 bits (Address 1000H to FFFFH) of program memory (FLASH ). A pro-

gram code placed on the internal RAM can be excutable when a certain procedure is executed ( See "2.3.2

Address trap reset ").

2.1.3 Data Memory (RAM)

Data memory consists of internal data memory (Internal FLASH or RAM). The TMP86FS49FG has 2Kbyte

(Address 0040H to 083FH) of internal RAM. The first 192 bytes (0040H to 00FFH) of the internal RAM are

located in the direct area; instructions with shorten operations are available against such an area.

The data memory contents become unstable when the power supply is turned on; therefore, the data memory

should be initialized by an initialization routine.

2.2 System Clock Controller

The system clock controller consists of a clock generator, a timing generator, and a standby controller.

Figure 2-2 System Colck Control

Example :Clears RAM to “00H”. (TMP86FS49FG)

HL, 0040H

; Start address setup

A, H

; Initial value (00H) setup

BC, 07FFH

;

SRAMCLR:

(HL), A

INC

DEC

JRS

F, SRAMCLR

TBTCR

SYSCR2

SYSCR1

XIN

XOUT

XTIN

XTOUT

0036H

0038H

0039H

Timing generator control register

Timing

generator

Standby controller

System clocks

Clock generator control

High-frequency

clock oscillator

Low-frequency

clock oscillator

Clock

generator

System control registers

TENTATIVE

TMP86FS49FG Datasheet(PDF) 12 Page - Toshiba Semiconductor

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