FDC37C78 datasheet(65/82 Pages) MICROCHIP

65 / 82 page

CR00

This register can only be accessed when the chip is in the Configuration Mode and after the CSR has

been initialized to 00H. The default value of this register after power up is 28H.

Table 34 - CR00

BIT NO.

BIT NAME

DESCRIPTION

0:1

Reserved

Read only. Read as 0

PDEN

Power Down and Idle enable.

0 nDS1pin=nDS1, nMTR1pin=nMTR1

1 nDS1pin=Power Down, nMTR1pin=Idle

FDC Power

A high level on this bit, supplies power to the FDC (default). A low

level on this bit puts the FDC in low power mode.

4, 6

Reserved

Read only. A read returns bits 4 and 6 as a 0.

OSC

Oscillator Control.

0 = Oscillator OFF

1 = Oscillator ON (default)

Valid

A high level on this software controlled bit can be used to indicate

that a valid configuration cycle has occurred. The control software

must take care to set this bit at the appropriate times. Set to zero

after power up. This bit has no effect on any other hardware in the

chip.

CR01

This register can only be accessed in the Configuration

Mode

and

after the CSR has been

initialized to 01H. The default value of this register after power up is 90H.

Table 35 - CR01

BIT NO.

BIT NAME

DESCRIPTION

0,1,2,3

Reserved

Read Only. A read returns a 0.

Reserved

Read Only. A read returns a 1.

5,6

Reserved

Read Only. A read returns a 0.

Lock CRx

A high level on this bit enables the reading and writing of CRxx

registers (Default). A low level on this bit disables the reading and

writing of all CRxx registers. Once set to 0, this bit can only be set

to 1 by a hard reset or power-up reset.

FDC37C78 Datasheet(PDF) 65 Page - Microchip Technology

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