PIC16F1459-ESSQTP datasheet(327/418 Pages) MICROCHIP

327 / 418 page

 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 327

PIC16(L)F1454/5/9

UCFG: USB CONFIGURATION REGISTER

R/W-0

U-0

R/W-0

UTEYE

Reserved

—

UPUEN(1)

Reserved

FSEN(1)

PPB<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

UTEYE:

USB Eye Pattern Test Enable bit

1 = Eye pattern test enabled

0 = Eye pattern test disabled

bit 5

Reserved:

Read as ‘0’. Maintain this bit clear

bit 4

UPUEN:

USB On-Chip Pull-up Enable bit(1)

1 = On-chip pull-up enabled (pull-up on D+ with FSEN = 1 or D- with FSEN = 0)

0 = On-chip pull-up disabled

bit 3

Reserved:

Read as ‘0’. Maintain this bit clear

bit 2

FSEN:

Full-Speed Enable bit(1)

1 = Full-speed device: controls transceiver edge rates; requires input clock at 48 MHz

0 = Low-speed device: controls transceiver edge rates; requires input clock at 6 MHz

bit 1-0

PPB<1:0>:

Ping-Pong Buffers Configuration bits

11 = Even/Odd ping-pong buffers enabled for Endpoints 1 to 15

10 = Even/Odd ping-pong buffers enabled for all endpoints

01 = Even/Odd ping-pong buffer enabled for OUT Endpoint 0

00 = Even/Odd ping-pong buffers disabled

Note 1:

The UPUEN, and FSEN bits should never be changed while the USB module is enabled. These values

must be preconfigured prior to enabling the module.

PIC16F1459-ESSQTP Datasheet(PDF) 327 Page - Microchip Technology

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