MCZ33903CD3EKSLASHR2 datasheet(39/106 Pages) FREESCALE

39 / 106 page

Analog Integrated Circuit Device Data



Freescale Semiconductor

33903/4/5

FUNCTIONAL DEVICE OPERATION

MODE AND STATE DESCRIPTION

FUNCTIONAL DEVICE OPERATION

MODE AND STATE DESCRIPTION

The device has several operation modes. The transitions

and conditions to enter or leave each mode are illustrated in

the state diagram.

INIT RESET

This mode is automatically entered after the device is

“powered on”. In this mode, the RST pin is asserted low, for

a duration of typically 1.0 ms. Control bits and flags are “set”

to their default reset condition. The BATFAIL is set to indicate

the device is coming from an unpowered condition, and all

previous device configurations are lost and “reset” the default

value. The duration of the INIT reset is typically 1.0 ms.

INIT reset mode is also entered from INIT mode if the

expected SPI command does not occur in due time (Ref. INIT

mode), and if the device is not in the debug mode.

INIT

This mode is automatically entered from the INIT Reset

mode. In this mode, the device must be configured via SPI

within a time of 256 ms max.

Four registers called INIT Wdog, INIT REG, INIT LIN I/O

and INIT MISC must be, and can only be configured during

INIT mode.

Other registers can be written in this and other modes.

Once the INIT register configuration is done, a SPI

Watchdog Refresh command must be sent in order to set the

device into Normal mode. If the SPI watchdog refresh does

not occur within the 256 ms period, the device will return into

INIT Reset mode for typically 1.0 ms, and then re enter into

INIT mode.

device status or to read back the INIT register configuration.

When INIT mode is left by a SPI watchdog refresh

command, it is only possible to re-enter the INIT mode using

a secured SPI command. In INIT mode, the CAN, LIN1, LIN2,

VAUX, I/O_x and Analog MUX functions are not operating.

The 5 V-CAN is also not operating, except if the Debug mode

is detected.

RESET

In this mode, the RST pin is asserted low. Reset mode is

entered from Normal mode, Normal Request mode, LP VDD

on mode and from the Flash mode when the watchdog is not

triggered, or if a VDD low condition is detected.

The duration of reset is typically 1.0 ms by default. You

can define a longer Reset pulse activation only when the

Reset mode is entered following a VDD low condition. Reset

pulse is always 1.0 ms, when reset mode is entered due to

wrong watchdog refresh command.

Reset mode can be entered via the secured SPI

command.

NORMAL REQUEST

This mode is automatically entered after RESET mode, or

after a Wake-up from LP VDD ON mode.

A watchdog refresh SPI command is necessary to

transition to NORMAL mode. The duration of the Normal

request mode is 256 ms when Normal Request mode is

entered after RESET mode. Different durations can be

selected by SPI when normal request is entered from LP VDD

ON mode.

If the watchdog refresh SPI command does not occur

within the 256 ms (or the shorter user defined time out), then

the device will enter into RESET mode for a duration of

typically 1.0 ms.

Note: in init reset, init, reset and normal request modes as

well as in LP modes, the VDD external PNP is disabled.

NORMAL

In this mode, all device functions are available. This mode

is entered by a SPI watchdog refresh command from Normal

Request mode, or from INIT mode.

During Normal mode, the device watchdog function is

operating, and a periodic watchdog refresh must occur.

When an incorrect or missing watchdog refresh command is

initiated, the device will enter into Reset mode.

While in Normal mode, the device can be set to LP modes

(LP VDD ON or LP VDD OFF) using the SPI command.

Dedicated, secured SPI commands must be used to enter

from Normal mode to Reset mode, INIT mode or Flash mode.

FLASH

In this mode, the software watchdog period is extended up

to typically 32 seconds. This allow programming of the MCU

flash memory while minimizing the software over head to

refresh the watchdog. The flash mode is entered by Secured

SPI command and is left by SPI command. Device will enter

into Reset mode. When an incorrect or missing watchdog

refresh command device will enter into Reset mode. An

interrupt can be generated at 50% of the watchdog period.

CAN interface operates in Flash mode to allow flash via

CAN bus, inside the vehicle.

DEBUG

Debug is a special operation mode of the device which

allows for easy software and hardware debugging. The

debug operation is detected after power up if the DBG pin is

set to 8.0 to 10 V range.

When debug is detected, all the software watchdog

operations are disabled: 256 ms of INIT mode, watchdog

refresh of Normal mode and Flash mode, Normal Request

time out (256 ms or user defined value) are not operating and

will not lead to transition into INIT reset or Reset mode.

When the device is in Debug mode, the SPI command can

be sent without any time constraints with respect to the

watchdog operation and the MCU program can be “halted” or

“paused” to verify proper operation.

MCZ33903CD3EK/R2 Datasheet(PDF) 39 Page - Freescale Semiconductor, Inc

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