MCZ33903CD3EKSLASHR2 datasheet(79/106 Pages) FREESCALE

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Analog Integrated Circuit Device Data



Freescale Semiconductor

33903/4/5

SERIAL PERIPHERAL INTERFACE

DETAIL OF CONTROL BITS AND REGISTER MAPPING

Table 34. CAN Register(41)

MOSI First byte [15-8]

[b_15 b_14] 10_000 [P/N]

MOSI Second Byte, bits 7-0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

01 10_ 000P

CAN mod[1]

CAN mod[0]

Slew[1]

Slew[0]

Wake-up 1/3

CAN int

Default state

Condition for default

note

POR

Bits

Description

b7 b6

CAN mod[1], CAN mod[0] - CAN interface mode control, Wake-up enable / disable

CAN interface in Sleep mode, CAN Wake-up disable.

CAN interface in receive only mode, CAN driver disable.

CAN interface is in Sleep mode, CAN Wake-up enable. In device LP mode,



CAN Wake-up is reported by device Wake-up. In device Normal mode, CAN Wake-up reported by INT.

CAN interface in transmit and receive mode.

b5 b4

Slew[1] Slew[0] - CAN driver slew rate selection

00/11

FAST

MEDIUM

SLOW

Wake-up 1/3 - Selection of CAN Wake-up mechanism

3 dominant pulses Wake-up mechanism

Single dominant pulse Wake-up mechanism

CAN INT - Select the CAN failure detection reporting

Select INT generation when a bus failure is fully identified and decoded (i.e. after 5 dominant pulses on TxCAN)

Select INT generation as soon as a bus failure is detected, event if not fully identified

Notes

41.

The first time the device is set to Normal mode, the CAN is in Sleep Wake-up enabled (bit7 = 1, bit 6 =0). The next time the device is

set in Normal mode, the CAN state is controlled by bits 7 and 6.

MCZ33903CD3EK/R2 Datasheet(PDF) 79 Page - Freescale Semiconductor, Inc

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