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PSD833F2 Datasheet(PDF) 103 Page - STMicroelectronics |
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PSD833F2 Datasheet(HTML) 103 Page - STMicroelectronics |
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103 / 128 page  PSD8XXFX AC/DC parameters Doc ID 7833 Rev 7 103/128 Figure 41. Asynchronous Reset / Preset Figure 42. Asynchronous Clock mode Timing (product term clock) tARP REGISTER OUTPUT tARPW RESET/PRESET INPUT AI02864 tCHA tCLA tCOA tHA tSA CLOCK INPUT REGISTERED OUTPUT AI02859 Table 52. CPLD macrocell asynchronous clock mode timing (5 V devices) Symbol Parameter Conditions -70 -90 -15 PT Aloc Turbo off Slew rate Unit Min Max Min Max Min Max fMAXA Maximum frequency External feedback 1/(tSA+tCOA) 38.4 26.32 21.27 MHz Maximum frequency Internal feedback (fCNTA) 1/(tSA+tCOA–10) 62.5 35.71 27.78 MHz Maximum frequency Pipelined data 1/(tCHA+tCLA) 71.4 41.67 35.71 MHz tSA Input setup time 7 8 12 + 2 + 10 ns tHA Input hold time 812 14 ns tCHA Clock input high time 9 12 15 + 10 ns tCLA Clock input low time 9 12 15 + 10 ns Obsolete Product(s) - Obsolete Product(s) |
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