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PSD833F2 Datasheet(PDF) 107 Page - STMicroelectronics |
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PSD833F2 Datasheet(HTML) 107 Page - STMicroelectronics |
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107 / 128 page  PSD8XXFX AC/DC parameters Doc ID 7833 Rev 7 107/128 tTHEH R/W setup time to Enable 6 10 18 ns tELTL R/W hold time After Enable 0 0 0 ns tAVPV Address input valid to Address output delay (5) 20 25 30 ns 1. Any input used to select an internal PSD function. 2. RD timing has the same timing as DS, LDS, and UDS signals. 3. RD and PSEN have the same timing. 4. RD timing has the same timing as DS, LDS, UDS, and PSEN signals. 5. In multiplexed mode, latched addresses generated from ADIO delay to address output on any port. Table 56. READ timing (5 V devices) (continued) Symbol Parameter Conditions -70 -90 -15 Turbo off Unit Min Max Min Max Min Max Table 57. READ timing (3 V devices) Symbol Parameter Conditions -12 -15 -20 Turbo off Unit Min Max Min Max Min Max tLVLX ALE or AS pulse width 26 26 30 ns tAVLX Address setup time (1) 910 12 ns tLXAX Address hold time (1) 912 14 ns tAVQV Address valid to data valid (1) 120 150 200 + 20 ns tSLQV CS valid to data valid 120 150 200 ns tRLQV RD to data valid 8-bit bus (2) 35 35 40 ns RD or PSEN to data valid 8-bit bus, 8031, 80251 (3) 45 50 55 ns tRHQX RD data hold time (4) 00 0 ns tRLRH RD pulse width 38 40 45 ns tRHQZ RD to data high-Z (4) 38 40 45 ns tEHEL E pulse width 40 45 52 ns tTHEH R/W setup time to enable 15 18 20 ns tELTL R/W hold time after enable 0 0 0 ns tAVPV Address input valid to address output delay (5) 33 35 40 ns 1. Any input used to select an internal PSD function. 2. RD timing has the same timing as DS, LDS, and UDS signals. 3. RD and PSEN have the same timing for 8031. 4. RD timing has the same timing as DS, LDS, UDS, and PSEN signals. 5. In multiplexed mode latched address generated from ADIO delay to address output on any port. Obsolete Product(s) - Obsolete Product(s) |
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