PSD833F2 datasheet(111/128 Pages) STMICROELECTRONICS

111 / 128 page

PSD8XXFX

AC/DC parameters

Doc ID 7833 Rev 7

111/128

Figure 46.

Peripheral I/O READ timing

The whole memory is programmed to 00h before erase.

The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.

tQXRH (PA)

tRLQV (PA)

tRLRH (PA)

tDVQV (PA)

tRHQZ (PA)

tSLQV (PA)

tAVQV (PA)

ADDRESS

DATA VALID

ALE /AS

A /D BUS

DATA ON PORT A

CSI

AI02897

Table 62.

Port A Peripheral Data mode READ timing (5 V devices)

Symbol

Parameter

Conditions

-70

-90

-15

Turbo

off

Unit

Min Max Min Max Min

Max

tAVQV–PA

Address valid to data valid

(1)

+ 10

tSLQV–PA

CSI valid to data valid

+ 10

tRLQV–PA

RD to data valid

(2)(3)

RD to data valid 8031 mode

tDVQV–PA

Data In to data out valid

tQXRH–PA

RD data hold time

tRLRH–PA

RD pulse width

(2)

tRHQZ–PA

RD to data high-Z

(2)

Any input used to select port A Data Peripheral mode.

RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).

Data is already stable on port A.

Obsolete

Product(s)

- Obsolete

Product(s)

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