PSD833F2 datasheet(112/128 Pages) STMICROELECTRONICS

112 / 128 page

AC/DC parameters

PSD8XXFX

112/128

Doc ID 7833 Rev 7

Figure 47.

Peripheral I/O WRITE timing

Table 63.

Port A Peripheral Data mode READ timing (3V devices)

Symbol

Parameter

Conditions

-12

-15

-20

Turbo

off

Unit

Min Max Min Max Min

Max

tAVQV–PA

Address valid to data valid

(1)

+ 20

tSLQV–PA

CSI valid to data valid

+ 20

tRLQV–PA

RD to data valid

(2)(3)

RD to data valid 8031 mode

tDVQV–PA

Data In to data Out valid

tQXRH–PA

RD data hold time

tRLRH–PA

RD pulse width

(2)

tRHQZ–PA

RD to data high-Z

(2)

Any input used to select port A Data Peripheral mode.

RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).

Data is already stable on port A.

tDVQV (PA)

tWLQV

(PA)

tWHQZ (PA)

ADDRESS

DATA OUT

A / D BUS

PORT A

DATA OUT

ALE /AS

AI02898

Table 64.

Port A Peripheral Data mode WRITE timing (5 V devices)

Symbol

Parameter

Conditions

-70

-90

-15

Unit

Min Max Min

Max Min Max

tWLQV–PA

WR to data propagation delay

(1)

tDVQV–PA

Data to port A data propagation delay

(2)

tWHQZ–PA

WR invalid to port A tri-state

(1)

WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.

Data stable on ADIO pins to data on port A.

Obsolete

Product(s)

- Obsolete

Product(s)

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