PSD833F2 datasheet(115/128 Pages) STMICROELECTRONICS

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PSD8XXFX

AC/DC parameters

Doc ID 7833 Rev 7

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Table 69.

ISC timing (3 V devices)

Symbol

Parameter

Conditions

-12

-15

-20

Unit

Min Max Min Max Min Max

tISCCF

Clock (TCK, PC1) frequency (except for

PLD)

(1)

MHz

tISCCH

Clock (TCK, PC1) high time (except for

PLD)

(1)

tISCCL

Clock (TCK, PC1) low time (except for

PLD)

(1)

tISCCFP

Clock (TCK, PC1) frequency (PLD only)

(2)

MHz

tISCCHP

Clock (TCK, PC1) high time (PLD only)

(2)

240

tISCCLP

Clock (TCK, PC1) low time (PLD only)

(2)

240

tISCPSU

ISC port setup time

tISCPH

ISC port hold up time

tISCPCO

ISC port clock to output

tISCPZV

ISC port high-Impedance to valid Output

tISCPVZ

ISC port valid Output to high-Impedance

For non-PLD Programming, Erase or in ISC by-pass mode.

For program or erase PLD only.

Table 70.

Power-down timing (5 V devices)

Symbol

Parameter

Conditions

-70

-90

-15

Unit

Min Max Min

Max Min Max

tLVDV

ALE access time from Power-down

150

tCLWH

Maximum delay from APD Enable to

Internal PDN valid signal

Using CLKIN

(PD1)

15 * tCLCL

(1)

µs

tCLCL is the period of CLKIN (PD1).

Table 71.

Power-down timing (3 V devices)

Symbol

Parameter

Conditions

-12

-15

-20

Unit

Min Max Min

Max Min Max

tLVDV

ALE access time from Power-down

145

150

200

tCLWH

Maximum Delay from APD Enable to

Internal PDN valid Signal

Using CLKIN

(PD1)

15 * tCLCL

(1)

µs

tCLCL is the period of CLKIN (PD1).

Obsolete

Product(s)

- Obsolete

Product(s)

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