PSD833F2 datasheet(113/128 Pages) STMICROELECTRONICS

113 / 128 page

PSD8XXFX

AC/DC parameters

Doc ID 7833 Rev 7

113/128

Figure 48.

Reset (RESET) timing

Table 65.

Port A Peripheral Data mode WRITE timing (3 V devices)

Symbol

Parameter

Conditions

-12

-15

-20

Unit

Min Max Min

Max Min Max

tWLQV–PA

WR to data propagation delay

(1)

tDVQV–PA

Data to port A data propagation delay

(2)

tWHQZ–PA

WR invalid to port A tri-state

(1)

WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.

Data stable on ADIO pins to data on port A.

tNLNH-PO

tOPR

AI02866b

RESET

tNLNH

tNLNH-A

tOPR

VCC

CC(min)

Power-On Reset

Warm Reset

Table 66.

Reset (RESET) timing (5 V devices)

Symbol

Parameter

Conditions

Min

Max

Unit

tNLNH

RESET active low time(1)

150

tNLNH–PO

Power-on Reset active low time

tNLNH–A

Warm Reset (on the PSD834Fx)(2)

µs

tOPR

RESET high to operational device

120

Reset (RESET) does not reset Flash memory program or erase cycles.

Warm reset aborts Flash memory program or erase cycles, and puts the device in READ mode.

Table 67.

Reset (RESET) timing (3 V devices)

Symbol

Parameter

Conditions

Min

Max

Unit

tNLNH

RESET active low time(1)

300

tNLNH–PO

Power-on Reset active low time

tNLNH–A

Warm Reset (on the PSD834Fx)(2)

µs

tOPR

RESET high to operational device

300

Reset (RESET) does not reset Flash memory program or erase cycles.

Warm reset aborts Flash memory program or erase cycles, and puts the device in READ mode.

Obsolete

Product(s)

- Obsolete

Product(s)

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