PIC18F4550ESOSQTP datasheet(116/430 Pages) MICROCHIP

116 / 430 page

PIC18F2455/2550/4455/4550

DS39632D-page 114

Preliminary

10.2

PORTB, TRISB and LATB

Registers

PORTB is an 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISB. Setting a

TRISB bit (= 1) will make the corresponding PORTB

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISB bit (= 0)

will make the corresponding PORTB pin an output (i.e.,

put the contents of the output latch on the selected pin).

The Data Latch register (LATB) is also memory

mapped. Read-modify-write operations on the LATB

PORTB.

Each of the PORTB pins has a weak internal pull-up. A

single control bit can turn on all the pull-ups. This is

performed by clearing bit, RBPU (INTCON2<7>). The

weak pull-up is automatically turned off when the port

pin is configured as an output. The pull-ups are

disabled on a Power-on Reset.

Four of the PORTB pins (RB7:RB4) have an interrupt-

on-change feature. Only pins configured as inputs can

cause this interrupt to occur. Any RB7:RB4 pin

configured as an output is excluded from the interrupt-

on-change comparison. The pins are compared with

the old value latched on the last read of PORTB. The

“mismatch” outputs of RB7:RB4 are ORed together to

generate the RB Port Change Interrupt with Flag bit,

RBIF (INTCON<0>).

The interrupt-on-change can be used to wake the

device from Sleep. The user, in the Interrupt Service

Routine, can clear the interrupt in the following manner:

Any read or write of PORTB (except with the

MOVFF

(ANY), PORTB

instruction). This will

end the mismatch condition.

Clear flag bit, RBIF.

A mismatch condition will continue to set flag bit, RBIF.

Reading PORTB will end the mismatch condition and

allow flag bit, RBIF, to be cleared.

The interrupt-on-change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt-on-change

feature. Polling of PORTB is not recommended while

using the interrupt-on-change feature.

Pins, RB2 and RB3, are multiplexed with the USB

peripheral and serve as the differential signal outputs

for an external USB transceiver (TRIS configuration).

Refer to Section 17.2.2.2 “External Transceiver” for

additional information on configuring the USB module

for operation with an external transceiver.

RB4 is multiplexed with CSSPP, the chip select

function for the Streaming Parallel Port (SPP) – TRIS

setting. Details of its operation are discussed in

Section 18.0 “Streaming Parallel Port”.

EXAMPLE 10-2:

INITIALIZING PORTB

Note:

On a Power-on Reset, RB4:RB0 are

configured as analog inputs by default and

read as ‘0’; RB7:RB5 are configured as

digital inputs.

By programming the Configuration bit,

PBADEN (CONFIG3H<1>), RB4:RB0 will

alternatively be configured as digital inputs

on POR.

CLRF

PORTB

; Initialize PORTB by

; clearing output

; data latches

CLRF

LATB

; Alternate method

; to clear output

; data latches

MOVLW

0Eh

; Set RB<4:0> as

MOVWF

ADCON1

; digital I/O pins

; (required if config bit

; PBADEN is set)

MOVLW

0CFh

; Value used to

; initialize data

; direction

MOVWF

TRISB

; Set RB<3:0> as inputs

; RB<5:4> as outputs

; RB<7:6> as inputs

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