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PIC18F4550ESOSQTP Datasheet(PDF) 118 Page - Microchip Technology |
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PIC18F4550ESOSQTP Datasheet(HTML) 118 Page - Microchip Technology |
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118 / 430 page  PIC18F2455/2550/4455/4550 DS39632D-page 116 Preliminary © 2007 Microchip Technology Inc. TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB RB6/KBI2/ PGC RB6 0 OUT DIG LATB<6> data output. 1 IN TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared. KBI2 1 IN TTL Interrupt-on-pin change. PGC x IN ST Serial execution (ICSP™) clock input for ICSP and ICD operation.(3) RB7/KBI3/ PGD RB7 0 OUT DIG LATB<7> data output. 1 IN TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared. KBI3 1 IN TTL Interrupt-on-pin change. PGD x OUT DIG Serial execution data output for ICSP and ICD operation.(3) x IN ST Serial execution data input for ICSP and ICD operation.(3) TABLE 10-3: PORTB I/O SUMMARY (CONTINUED) Pin Function TRIS Setting I/O I/O Type Description Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, I2C/SMB = I2C/SMBus input buffer, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option) Note 1: Configuration on POR is determined by PBADEN Configuration bit. Pins are configured as analog inputs when PBADEN is set and digital inputs when PBADEN is cleared. 2: Alternate pin assignment for CCP2 when CCP2MX = 0. Default assignment is RC1. 3: All other pin functions are disabled when ICSP™ or ICD operation is enabled. 4: 40/44-pin devices only. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 54 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 54 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 54 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP —RBIP 51 INTCON3 INT2IP INT1IP —INT2IE INT1IE — INT2IF INT1IF 51 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 52 SPPCON(1) — — — — — — SPPOWN SPPEN 55 SPPCFG(1) CLKCFG1 CLKCFG0 CSEN CLK1EN WS3 WS2 WS1 WS0 55 UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND —55 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB. Note 1: These registers are unimplemented on 28-pin devices. |
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