 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
PIC18F4550ESOSQTP Datasheet(PDF) 120 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
PIC18F4550ESOSQTP Datasheet(HTML) 120 Page - Microchip Technology |
|
|
120 / 430 page  PIC18F2455/2550/4455/4550 DS39632D-page 118 Preliminary © 2007 Microchip Technology Inc. TABLE 10-5: PORTC I/O SUMMARY Pin Function TRIS Setting I/O I/O Type Description RC0/T1OSO/ T13CKI RC0 0 OUT DIG LATC<0> data output. 1 IN ST PORTC<0> data input. T1OSO x OUT ANA Timer1 oscillator output; enabled when Timer1 oscillator enabled. Disables digital I/O. T13CKI 1 IN ST Timer1/Timer3 counter input. RC1/T1OSI/ CCP2/UOE RC1 0 OUT DIG LATC<1> data output. 1 IN ST PORTC<1> data input. T1OSI x IN ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled. Disables digital I/O. CCP2(1) 0 OUT DIG CCP2 Compare and PWM output; takes priority over port data. 1 IN ST CCP2 Capture input. UOE 0 OUT DIG External USB transceiver OE output. RC2/CCP1/ P1A RC2 0 OUT DIG LATC<2> data output. 1 IN ST PORTC<2> data input. CCP1 0 OUT DIG ECCP1 Compare and PWM output; takes priority over port data. 1 IN ST ECCP1 Capture input. P1A(3) 0 OUT DIG ECCP1 Enhanced PWM output, channel A; takes priority over port data. May be configured for tri-state during Enhanced PWM shutdown events. RC4/D-/VM RC4 —(2) IN TTL PORTC<4> data input; disabled when USB module or on-chip transceiver are enabled. D- —(2) OUT XCVR USB bus differential minus line output (internal transceiver). —(2) IN XCVR USB bus differential minus line input (internal transceiver). VM —(2) IN TTL External USB transceiver VM input. RC5/D+/VP RC5 —(2) IN TTL PORTC<5> data input; disabled when USB module or on-chip transceiver are enabled. D+ —(2) OUT XCVR USB bus differential plus line output (internal transceiver). —(2) IN XCVR USB bus differential plus line input (internal transceiver). VP —(2) IN TTL External USB transceiver VP input. RC6/TX/CK RC6 0 OUT DIG LATC<6> data output. 1 IN ST PORTC<6> data input. TX 0 OUT DIG Asynchronous serial transmit data output (EUSART module); takes priority over port data. User must configure as output. CK 0 OUT DIG Synchronous serial clock output (EUSART module); takes priority over port data. 1 IN ST Synchronous serial clock input (EUSART module). Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, XCVR = USB transceiver, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option) Note 1: Default pin assignment. Alternate pin assignment is RB3 (when CCP2MX = 0). 2: RC4 and RC5 do not have corresponding TRISC bits. In Port mode, these pins are input only. USB data direction is determined by the USB configuration. 3: 40/44-pin devices only. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
