PIC18F4550ESOSQTP datasheet(122/430 Pages) MICROCHIP

122 / 430 page

PIC18F2455/2550/4455/4550

DS39632D-page 120

Preliminary

10.4

PORTD, TRISD and LATD

Registers

PORTD is an 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISD. Setting a

TRISD bit (= 1) will make the corresponding PORTD

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISD bit (= 0)

will make the corresponding PORTD pin an output (i.e.,

put the contents of the output latch on the selected pin).

The Data Latch register (LATD) is also memory

mapped. Read-modify-write operations on the LATD

PORTD.

All pins on PORTD are implemented with Schmitt

Trigger

input

buffers.

Each

individually

configurable as an input or output.

Each of the PORTD pins has a weak internal pull-up. A

single control bit, RDPU (PORTE<7>), can turn on all

the pull-ups. This is performed by setting RDPU. The

weak pull-up is automatically turned off when the port

pin is configured as a digital output or as one of the

other

multiplexed

peripherals.

The

pull-ups

are

disabled on a Power-on Reset. The PORTE register is

shown in Section 10.5 “PORTE, TRISE and LATE

Registers”.

Three of the PORTD pins are multiplexed with outputs,

P1B, P1C and P1D, of the Enhanced CCP module. The

operation of these additional PWM output pins is

covered in greater detail in Section 16.0 “Enhanced

Capture/Compare/PWM (ECCP) Module”.

PORTD can also be configured as an 8-bit wide

Streaming Parallel Port (SPP). In this mode, the input

buffers are TTL. For additional information on con-

figuration and uses of the SPP, see Section 18.0

“Streaming Parallel Port”.

EXAMPLE 10-4:

INITIALIZING PORTD

Note:

PORTD is only available on 40/44-pin

devices.

Note:

On a Power-on Reset, these pins are

configured as digital inputs.

Note:

When the Enhanced PWM mode is used

with either dual or quad outputs, the MSSP

functions of PORTD are automatically

disabled.

CLRF

PORTD

; Initialize PORTD by

; clearing output

; data latches

CLRF

LATD

; Alternate method

; to clear output

; data latches

MOVLW

0CFh

; Value used to

; initialize data

; direction

MOVWF

TRISD

; Set RD<3:0> as inputs

; RD<5:4> as outputs

; RD<7:6> as inputs

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