AS3543 datasheet(72/92 Pages) AMSCO

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AS3543 3v2

Data Sheet - R e g i s t e r D e f i n i t i o n

3:2

DRIVE_XRES<1:0>

R/W

Sets the XRES output pin to open-drain, push-pull or tri-state

and sets various driving strengths

00: 6mA open-drain output

01: 6mA push-pull output

10: 1mA push-pull output

11: HiZ, stri-state

1:0

MUX_XRES<1:0>

R/W

Multiplexes various digital signals to the XRES output pin

00: XRES, active low reset signal

01: CLK32k, 32kHz RTC oszillator output

10: CLKINT1, internal clock signal, see Clk_Cntr regsiter

11: PWM, PMW_Cntr register

Table 69. Out_Cntr2 Register

Name

Base

Default

Out_Cntr2

2-wire serial

00h

Offset: 1Ah-2

Q24M and Q32k Output Control Register

This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first.

This register is reset at a AVDD27-POR.

Bit

Bit Name

Default

Access

Bit Description

7:6

DRIVE_Q24M<1:0>

R/W

Sets the PWGD output pin to push-pull or tri-state and sets

various driving strengths

00: 6mA push-pull output

01: HiZ, stri-state

10: 2mA push-pull output

11: 1mA push-pull output

5:4

MUX_Q24M<1:0>

R/W

Multiplexes various digital signals to the PWGD output pin

00: CLK24M, 24MHz oszillator output signal

01: CLKINT1, internal clock signal, see Clk_Cntr regsiter

10: CLKINT2, internal clock signal, see Clk_Cntr regsiter

11: PWM, PMW_Cntr register

3:2

DRIVE_Q32k<1:0>

R/W

Sets the XRES output pin to push-pull or tri-state and sets

various driving strengths

00: 6mA push-pull output

01: HiZ, stri-state

10: 2mA push-pull output

11: 1mA push-pull output

1:0

MUX_Q32k<1:0>

R/W

Multiplexes various digital signals to the XRES output pin

00: CLK32k, 32kHz RTC oszillator output signal

01: CLKINT1, internal clock signal, see Clk_Cntr regsiter

10: CLKINT2, internal clock signal, see Clk_Cntr regsiter

11: PWM, PMW_Cntr register

Table 68. Out_Cntr1 Register

Name

Base

Default

Out_Cntr1

2-wire serial

00h

Offset: 1Ah-1

PWGD and XRES Output Control Register

This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first.

This register is reset at a AVDD27-POR.

Bit

Bit Name

Default

Access

Bit Description

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