AS3543 datasheet(74/92 Pages) AMSCO

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Revision 1.11

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AS3543 3v2

Data Sheet - R e g i s t e r D e f i n i t i o n

Table 72. Clk_Cntr Register

Name

Base

Default

Clk_Cntr

2-wire serial

00h

Offset: 1Ah-5

Clock Control Register

This is an extended register and needs to be enabled by writing 101b to Reg. 1Ch first.

This register is reset at a AVDD27-POR.

Bit

Bit Name

Default

Access

Bit Description

7:6

CLKINT2<1:0>

R/W

Selects the CLKINT2 input source. Note, this is an internal

clock, which can be multiplexed to one of the GPIO ouptus.

00: CLKPLL, internal PLL clock

01: CLKlogdim, clock used for dimming the DCDC15

10: LOW, drives the signal to logic “0”

11: HIGH, drives the signal to logic “1”

5:4

CLKINT1<1:0>

R/W

Selects the CLKINT1 frequency. Note, this is an internal clock,

which can be multiplexed to one of the GPIO ouptus.

00: 2MHz

01: 887kHz

10: 1kHz

11: 125Hz

3:2

CLK24M<1:0>

R/W

Selects the CLK24M frequency, clock of 24MHz oszillator

00: OSC24MHz, oszillator frequency

01: OSC24MHz_div2, oszillator frequency divided by 2

10: OSC24MHz_div4, oszillator frequency divided by 4

11: OSC24MHz_PD, OSC24M is set to power down

1:0

CLK32k<1:0>

R/W

Selects the CLK32k frequnecy, clock of 32kHz RTC oszillator

00: OSC32kHz, RTC oszillator frequency

01: 1Hz

10: LOW, drives the signal to logic “0”

11: HIGH, drives the signal to logic “1”

Table 73. PWM_Cntr Register

Name

Base

Default

PWM_Cntr

2-wire serial

00h

Offset: 1Ah-6

PWM Control Register

This is an extended register and needs to be enabled by writing 110b to Reg. 1Ch first.

This register is reset at a AVDD27-POR.

Bit

Bit Name

Default

Access

Bit Description

PWM_INVERT

R/W

PWM output polarity

0: not inverted

1: inverted

6:0

PWM_CYCLE<6:0>

0000000

R/W

Sets the PWM duty cycle

0: no pulses

1-127: duty cycle = PWM_CYCLE * 0,39%

AS3543 Datasheet(PDF) 74 Page - ams AG

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