AS3543 datasheet(44/92 Pages) AMSCO

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AS3543 3v2

Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s

10 Detailed Description - SYSTEM Functions

10.1

SYSTEM

10.1.1 General

The system block handles the power up, power down and regulator voltage settings of the AFE.

The PWGD and XRES outputs can be configured to operate in push/pull (2 different driver strengths) open-drain mode

or to be tri-state. For a more detailed description of the GPIO functionality of these pins please refer to chapter GPIO

Pins on page 50.

10.1.2 Power Up/Down Conditions

The chip powers up when one of the following condition is true:

The chip automatically shuts off if one of the following conditions arises:

Table 28. Power UP Conditions

Source

Description

PWRUP PwUp

ON_KEY High Level at PRWUP pin of >= 1/3 BVDD

CHGIN PwUp

Charger Plug-In … High level at CHGIN pin of >= 4.0V

VBUS PwUp

USB Plug-In …. High level at VBUS pin of >= 4.5V

WAKEUP PwUp

Wake-Up Timer power-up on RTC clock

MCLK PwUp

ON_KEY High Level at MCLK pin of >= 1/3 BVDD

Table 29. Power DOWN Conditions

Source

Description

SERIF MAJOR PwDn

Power-Down

by SERIF writing 0h to register 20h

This Power-Down clears wake-up as well.

Emergency PwDn

Power-Down

if PWRUP pin is HIGH for 10sec.

This time can be reduced to 5sec with bit 7 in register 21h.

Wake-Up PwDn

write 4h to reg. 1Ch and 0h to reg. 1Ah … disable heartbeat source

Write 3 times to reg.22h to define wake-up time;

Power-Down

by heartbeat without source by writing 9h to reg. 20h

Heartbeat PwDn

write 4h to reg. 1Ch and 4h/8h or Ch to reg. 1Ah … select HBT source

write 9h to reg. 20h … enable heartbeat with source

Power-Down

if no edge on the selected HBT source is seen for 500ms.

SERIF Watch-Dog

PwDn

write 3h to reg. 20h … enable SERIF watch-dog

Power-Down

if no SERIF read is seen for 500ms.

Junction-Temp PwDn

Power-Down

if junction temperature rises up to 140degC.

This threshold can be lowered with bits <4:0> in reg 21h.

This supervisor can be disabled with bit 2 in reg. 20h.

BVDD LOW PwDn

Power-Down

if AVDD27 LDO has 10% under-voltage for more than 680us.

This supervisor can get disabled with bit 6 in reg. 21h.

PVDD1 LOW PwDn

Power-Down

if enabled with bit 1 in reg. 23h and

PVDD1 LDO has 10% under-voltage for more than 680us.

PVDD2 LOW PwDn

Power-Down

if enabled with bit 3 in reg. 23h and

PVDD2 LDO has 10% under-voltage for more than 680us.

CVDD1 LOW PwDn

Power-Down

if enabled with bit 7 in reg. 23h and

CVDD1 DCDC has 10% under-voltage for more than 680us.

CVDD2 LOW PwDn

Power-Down

if enabled with bit 1 in reg. 24h and

CVDD2 DCDC has 10% under-voltage for more than 680us.

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