AS3543 datasheet(81/92 Pages) AMSCO

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AS3543 3v2

Data Sheet - R e g i s t e r D e f i n i t i o n

Table 83. Second Interrupt Register

Name

Base

Default

IRQENRD_1

2-wire serial

00h

Offset: 24h

Second Interrupt Register

Please be aware that writing to this register will enable/disable the

corresponding interrupts, while reading gets the actual interrupt status and

will clear the register at the same time. It is not possible to read back the

interrupt enable/disable settings. This register is reset at a AVDD27-POR.

Bit

Bit Name

Default

Access

Bit Description

PWRUP_IRQ

Enables interrupt which is invoked whenever a high signal at

the PWRUP input pin occurs

0: disable

1: enable

This bit is set whenever a high level of min. BVDD/3 at the

PWRUP input pin occurs (PWRUP pin is commonly connected

to the power-up button)

WAKEUP_IRQ

Enables interrupt which is invoked whenever a wake-up from

RTC wake-up counter occurs

0: disable

1: enable

This bit is set when a wake-up has been invoked by the RTC

wake-up counter.

MCLK_IRQ

Enables interrupt which is invoked whenever a high signal at

the MCLK input pin occurs

0: disable

1: enable

This bit is set whenever a high level of min. BVDD/3 at the

MCLK input pin occurs (MCLK pin can be used as alternative

power-up button)

4:2

n/a

CVDD2_SD

Invokes shut-down of AFE when a –10% under-voltage spike

at CVDD2 occurs

0: disable

1: enable

CVDD2_under

This bit is set when a –5% under-voltage at CVDD2 occurs

CVDD2_IRQ

Enables interrupt for over-voltage/under-voltage supervision of

CVDD2

0: disable

1: enable

CVDD2_over

This bit is set when a +8% over-voltage at CVDD2 occurs

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