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AS3543 Datasheet(PDF) 57 Page - ams AG |
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AS3543 Datasheet(HTML) 57 Page - ams AG |
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57 / 92 page  1Ch PMU_Enable DC_TEST_MUX <3:0> 0: open; 1: AVDD27; 2: AVDD17; 3: PVDD1; 4: PVDD2; 5: CVDD1; 6: CVDD2; 7: RVDD; 8: FVDD; 9: PWGD; A-F: not defined PMU_GATE PMU_WR_ENABLE <2:0> SubRegister addresses for registers: 0x17: DCDC regulators 0x18: LDOs regulators 0x19: Charger 0x1A: IO_clock_control 0x1B: BackLight_DCDC System Register 20h SYSTEM Design_Version<3:0> HB_WD_ON JTEMP_OFF I2C_WD_ON PWR_HOLD 21h SUPERVISOR SD_TIME 0: 10s; 1: 5s BVDDlow_SD_ OFF VDD27-10% - JTEMP_SUP<4:0> Temp_ShutDown = 140°C - JTEMP_SUP*5°C -> (140°C...- 15°C) TEmp_IRQ = 120°C - JTEMP_SUP*5°C -> (120°C...-35°C) 22h RAM & WakeUp 1st write/read: WAKE_UP_BYTE_0 128s 64s 32s 16s 8s 4s 2s 1s 2nd write/read: WAKE_UP_BYTE_1 32ks 16ks 8ks 4ks 2ks 1ks 512s 256s 3rd write/read: WAKE_UP_BYTE_2 WAKEUP_ ON 4Ms 2Ms 1Ms 512ks 256ks 128ks 64ks 4th to 19th write/read: non volatile memory bytes<0:15> SRAM_128<0:15> 23h IRQENRD_0 CVDD1_SD CVDD1_IRQ - - PVDD2_SD PVDD2_IRQ PVDD1_SD PVDD1_IRQ CVDD1_under CVDD1_over - - PVDD2_under PVDD2_over PVDD1_under PVDD1_over 24h IRQENRD_1 PWRUP_IRQ WAKEUP_IRQ MCLK_IRQ - - - CVDD2_SD CVDD2_IRQ CVDD2_under CVDD2_over 25h IRQENRD_2 BATTEMP_IRQ - - CHG_IRQ - USB_IRQ RTC_WD BVDD_LOW CHG_EOC CHG_CON CHG_changed USB_CON USB_changed 26h IRQENRD_3 JTEMP_HIGH - HP_OVC - I2S_IRQ VOXM_IRQ MIC_CON HPH_CON I2S_status I2S_changed 27h IRQENRD_4 T_DEB<1:0> 0: 512ms; 1: 256ms; 2: 128ms; 3: 8ms AVDD27_IRQ DCDC15_IRQ - REM_DET RTC_UPDATE ADC_EOC AVDD27_under DCDC15_over 28h RTC_Cntr Free_Bits<3:0> to be used for application purpose - RTC_ON OSC_ON 29h RTC_Time IRQ_MIN TRTC<6:0> 2Ah RTC_0 QRTC<7:0> Table 43. I2C Register Overview Addr Name b7 b6 b5 b4 b3 b2 b1 b0 |
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