M25P64-VMF6TPBA datasheet(26/55 Pages) NUMONYX

26 / 55 page

Instructions

M25P64

26/55

Figure 10.

Read Identification (RDID) instruction sequence and data-out sequence

6.4

Read Status Register (RDSR)

The Read Status Register (RDSR) instruction allows the Status Register to be read. The

Status Register may be read at any time, even while a Program, Erase or Write Status

check the Write In Progress (WIP) bit before sending a new instruction to the device. It is

also possible to read the Status Register continuously, as shown in Figure 11.

The status and control bits of the Status Register are as follows:

6.4.1

WIP bit

The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status

0 no such cycle is in progress.

6.4.2

WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable

Latch is reset and no Write Status Register, Program or Erase instruction is accepted.

6.4.3

BP2, BP1, BP0 bits

The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to

be software protected against Program and Erase instructions. These bits are written with

DQ0

456789 10 11 12 13 14 15

Instruction

AI06809d

DQ1

Manufacturer identification

High Impedance

MSB

Device identification

MSB

15 14 13

16 17 18

28 29 30 31

MSB

UID

Table 6.

Status Register format

SRWD

BP2

BP1

BP0

WEL

WIP

Status Register Write Protect

Block Protect Bits

Write Enable Latch Bit

Write In Progress Bit

M25P64-VMF6TPBA Datasheet(PDF) 26 Page - Numonyx B.V

M25P64-VMF6TPBA Datasheet(HTML) 26 Page - Numonyx B.V

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

Datasheet Download

Link URL