M25P64-VMF6TPBA datasheet(27/55 Pages) NUMONYX

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M25P64

Instructions

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the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2,

BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 2) becomes

protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect

(BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not

been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2,

BP1, BP0) bits are 0.

6.4.4

SRWD bit

The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write

Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and Write Protect

(W/VPP) signal allow the device to be put in the Hardware Protected mode (when the Status

this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become

read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for

execution.

Figure 11.

Read Status Register (RDSR) instruction sequence and data-out

sequence

3456789 10 11 12 13 14 15

Instruction

AI02031E

6543210

Status Register Out

High Impedance

MSB

6543210

Status Register Out

MSB

M25P64-VMF6TPBA Datasheet(PDF) 27 Page - Numonyx B.V