82375EB datasheet(13/131 Pages) INTEL

13 / 131 page

82375EBSB

The DMA controller supports an enhanced feature called scattergather This feature provides the capability

of transferring multiple buffers between memory and IO without CPU intervention In scattergather mode

the DMA can read the memory address and word count from an array of buffer descriptors located in main

memory called the scattergather descriptor (SGD) table This allows the DMA controller to sustain DMA

transfers until all of the buffers in the SGD table are handled

Interrupt Controller

The ESC contains an EISA compatible interrupt controller that incorporates the functionality of two 82C59

Interrupt Controllers The two interrupt controllers are cascaded providing 14 external and two internal inter-

rupts

Advanced Programmable Interrupt Controller (APIC)

In addition to the standard EISA compatible interrupt controller described above the ESC incorporates the

Advanced Programmable Interrupt Controller (APIC) While the standard interrupt controller is intended for use

in a uni-processor system APIC can be used in either a uni-processor or multi-processor system APIC

provides multi-processor interrupt management and incorporates both static and dynamic symmetric interrupt

distribution across all processors In systems with multiple IO subsystems each subsystem can have its own

set of interrupts

TimerCounter

The ESC provides two 82C54 compatible timers (Timer 1 and Timer 2) The counters in Timer 1 support the

system timer interrupt (IRQ0 ) refresh request and a speaker tone output (SPKR) The counters in Timer 2

support fail-safe time-out functions and the CPU speed control

Integrated Support Logic

To minimize the chip count for board designs the ESC incorporates a number of extended features The ESC

provides support for ALTA20 (Fast A20GATE) and ALTRST with IO Port 92h The ESC generates the control

signals for SA address buffers and X-Bus buffer The ESC also provides chip selects for BIOS the keyboard

controller the floppy disk controller and three general purpose devices Support for generating chip selects

with an external decoder is provided for IDE a parallel port and a serial port The ESC provides support for a

PCAT compatible coprocessor interface and IRQ13 generation

Power Management

Extensive power management capability permits a system to operate in a low power state without being

powered down Once in the low power state (called ‘‘Fast Off’’ state) the computer appears to be off For

example the SMM code could turn off the CRT line printer hard disk drive’s spindle motor and fans In

addition the CPU’s clock can be governed To the user the machine appears to be in the off state However

the system is actually in an extremely low power state that still permits the CPU to function and maintain

communication connections normally associated with today’s desktops (eg LAN Modem or FAX) Program-

mable options provide power management flexibility For example various system events can be programmed

to place the system in the low power state or break events can be programmed to wake the system up

82375EB Datasheet(PDF) 13 Page - Intel Corporation