82375EB datasheet(46/131 Pages) INTEL

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82375EBSB

3124 IOREGN 41

EISA-TO-PCI IO REGION ADDRESS REGISTERS

Address Offset

70-73h (IO Region 1)

74-77h (IO Region 2)

78-7Bh (IO Region 3)

7C-7Fh (IO Region 4)

Default value

0000FFFCh

Attribute

ReadWrite

Size

32 bits

These 32-bit registers provide four windows for EISA-to-PCI IO accesses The windows define positively

decoded programmable address regions for mapping EISA IO space to the corresponding PCI IO space

Each register determines the starting and limit addresses of the particular region within the 64 KByte PCI IO

space The base and limit addresses can be aligned on any Dword boundary and each region can be sized in

Dword increments (32-bits) up to the theoretical maximum size of 64 KByte Default values for the base and

limit fields ensure that the regions are initially disabled

The IO regions are selected based on the following formula Base Address s address s Limit Address

Bit

Description

3118

IO Region Limit Address

For EISA-to-PCI IO accesses bits 3118 correspond to address lines

LA 152 on the EISA Bus and AD 152 on the PCI Bus This field determines the limit address of

the region within the 64 KByte PCI IO space

1716

Reserved

152

IO Region Base Address

For EISA-to-PCI IO accesses bits 152 correspond to address lines

LA 152 on the EISA Bus and AD 152 on the PCI Bus This field determines the starting address

of the region within the 65 KByte PCI IO space

Reserved

3125 BTMRBIOS TIMER BASE ADDRESS REGISTER

Address Offset

80 – 81h

Default value

0078h

Attribute

ReadWrite

Size

16 bits

This 16-bit register determines the base address for the BIOS Timer Register located in PCI IO space The

BIOS Timer resides in the PCEB and is the only internal resource mapped to PCI IO space The base address

can be set at Dword boundaries anywhere in the 64 KByte PCI IO space This register also provides the BIOS

Timer access enabledisable control bit

82375EB Datasheet(PDF) 46 Page - Intel Corporation

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